公开(公告)号：US10720521B2

公开(公告)日：2020-07-21

申请号：US16359345

申请日：2019-03-20

Applicant: Industrial Technology Research Institute

Inventor： Jung-Tse Tsai ,  Po-Chun Yeh ,  Chien-Hua Hsu ,  Po-Tsung Tu

IPC: H01L21/338 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/12

Abstract: An enhancement mode GaN transistor is provided, which includes a GaN layer, a quantum well structure, a gate, a source a drain and a first barrier layer. The quantum well structure is disposed on the upper surface of the GaN layer. The gate is disposed on the quantum well structure. The source is disposed on one end of the upper surface of the GaN layer. The drain is disposed on the other end of the upper surface of the GaN layer. The first barrier layer is disposed on the upper surface of the GaN layer and extends to the lateral surfaces of the quantum well structure.