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公开(公告)号:US20250155528A1
公开(公告)日:2025-05-15
申请号:US18510084
申请日:2023-11-15
Applicant: Infineon Technologies AG
Inventor: Dan Ioan Dumitru STOICA , Ilie-Ionut CRISTEA , Armin SATZ , Georg KAFFL
Abstract: A magnetic field sensor chip includes an input terminal configured to receive an external bias current from an external current source; an internal current generator configured to split the external bias current into a plurality of internal bias currents, including a first internal bias current and a second internal bias current; a Hall sensor configured to be biased by the first internal bias current and set at a first operating point based on the first internal bias current, wherein the Hall sensor is further configured to generate a sensor signal based on a magnetic field and the first operating point; and an amplifier configured to be biased by the second internal bias current and set at a second operating point based on the second internal bias current. The amplifier is configured to amplify the sensor signal into an amplified sensor signal based on the second operating point.
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公开(公告)号:US20250125692A1
公开(公告)日:2025-04-17
申请号:US18488651
申请日:2023-10-17
Applicant: Infineon Technologies AG
Inventor: Georg KAFFL , Benjamin KOLLMITZER
IPC: H02K11/27 , G01B7/30 , G01R35/00 , H02K11/215
Abstract: A system may include a first sensor and a second sensor. The second sensor may be configured to receive a trigger associated with synchronizing sampling of a second sensor signal with sampling of a first sensor signal associated with the first sensor. The second sensor may be configured to obtain a second sample associated with a second sensor signal based on the trigger, wherein the second sample is synchronous with a first sample associated with the first sensor signal. The second sensor may be configured to transmit an output signal that includes information associated with the second sample.
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公开(公告)号:US20250093904A1
公开(公告)日:2025-03-20
申请号:US18467955
申请日:2023-09-15
Applicant: Infineon Technologies AG
Inventor: Georg KAFFL , Benjamin KOLLMITZER , Ahsan ALI
Abstract: An integrated circuit (IC) includes an internal clock source configured to generate an internal clock signal; a communication interface configured to receive an external clock signal from an external clock source and a communication frame signal that signals a communication frame during which data communication between the IC and the external clock source is enabled, wherein the external clock signal and the communication frame signal are received in parallel; and a clock monitoring circuit configured to monitor the internal clock signal based on the external clock signal. The clock monitoring circuit is configured to compare the internal clock signal and the external clock signal during the communication frame, and generate a timing error signal if a frequency of the internal clock signal does not satisfy a predetermined threshold relative to a frequency of the external clock signal.
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