公开(公告)号：US11493982B2

公开(公告)日：2022-11-08

申请号：US17152862

申请日：2021-01-20

Applicant: Infineon Technologies AG

Inventor： Konstantin Ivanchenko ,  Cristian Garbossa ,  Bejoy Mathews

IPC: G06F1/3234 ,  G06F1/3206

Abstract: Systems, methods, and circuitries are provided for controlling a microcontroller (MCU) on a per-application basis. A control system includes a microcontroller unit (MCU) including a first application group and a second application group. The first application group includes at least one hardware component not associated with the second application group. The control system includes a power management integrated circuit (PMIC). The PMIC includes monitoring circuitry configured to monitor the first application group to detect a first application group fault condition and monitor the second application group to detect a second application group fault condition. Based on the monitoring, the PMIC provides a first reset signal to the first application group that does not reset the second application group or provides a second reset signal to the second application group that does not reset the first application group.

公开(公告)号：US20220229486A1

公开(公告)日：2022-07-21

申请号：US17152862

申请日：2021-01-20

Applicant: Infineon Technologies AG

Inventor： Konstantin Ivanchenko ,  Cristian Garbossa ,  Bejoy Mathews

IPC: G06F1/3234 ,  G06F1/3206

Abstract: Systems, methods, and circuitries are provided for controlling a microcontroller (MCU) on a per-application basis. A control system includes a microcontroller unit (MCU) including a first application group and a second application group. The first application group includes at least one hardware component not associated with the second application group. The control system includes a power management integrated circuit (PMIC). The PMIC includes monitoring circuitry configured to monitor the first application group to detect a first application group fault condition and monitor the second application group to detect a second application group fault condition. Based on the monitoring, the PMIC provides a first reset signal to the first application group that does not reset the second application group or provides a second reset signal to the second application group that does not reset the first application group.

公开(公告)号：US12007820B2

公开(公告)日：2024-06-11

申请号：US17337650

申请日：2021-06-03

Applicant: Infineon Technologies AG

Inventor： Konstantin Ivanchenko ,  Petru Bacinski ,  Bejoy Mathews

IPC: G06F1/30 ,  G06F11/07 ,  G06F11/20

CPC classification number: G06F1/30 ,  G06F11/0721 ,  G06F11/079 ,  G06F11/2015

Abstract: A controller chip includes a first cluster including one or more first controller units, a first power supply grid, a first clock tree structure to supply one or more clock signals, and at least a first power supply input. A second cluster includes one or more second controller units, a second power supply grid, a second clock tree structure to supply one or more clock signals, and at least a second power supply input. A monitoring cluster includes a monitoring circuit configured to: monitor the power supply and the clock signal supply of each of the first cluster and second cluster, and in the event of determining at least one of a power supply failure or a clock signal supply failure in one cluster of the first cluster or the second cluster, indicate the failure to the other cluster to take one or more actions.

公开(公告)号：US20210382536A1

公开(公告)日：2021-12-09

申请号：US17337650

申请日：2021-06-03

Applicant: Infineon Technologies AG

Inventor： Konstantin Ivanchenko ,  Petru Bacinski ,  Bejoy Mathews

IPC: G06F1/30 ,  G06F11/07

Abstract: A controller chip includes a first cluster including one or more first controller units, a first power supply grid, a first clock tree structure to supply one or more clock signals, and at least a first power supply input. A second cluster includes one or more second controller units, a second power supply grid, a second clock tree structure to supply one or more clock signals, and at least a second power supply input. A monitoring cluster includes a monitoring circuit configured to: monitor the power supply and the clock signal supply of each of the first cluster and second cluster, and in the event of determining at least one of a power supply failure or a clock signal supply failure in one cluster of the first cluster or the second cluster, indicate the failure to the other cluster to take one or more actions.