公开(公告)号：US11237990B2

公开(公告)日：2022-02-01

申请号：US16901517

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Alexander Slota ,  James Coleman ,  Rajkumar Khandelwal ,  Anil Kumar

IPC: G06F13/28 ,  G06F13/12 ,  G06F12/1081

Abstract: System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.

公开(公告)号：US10684963B2

公开(公告)日：2020-06-16

申请号：US16236057

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Alexander Slota ,  James Coleman ,  Rajkumar Khandelwal ,  Anil Kumar

IPC: G06F13/28 ,  G06F13/12 ,  G06F12/1081

Abstract: System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.

公开(公告)号：US12301697B2

公开(公告)日：2025-05-13

申请号：US17132058

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Vikram Dadwal ,  James Coleman ,  Alexander Slota

IPC: G06F1/12 ,  G06F1/14 ,  H04L7/04

Abstract: Systems and techniques for an heterogeneous clock management solution for industrial systems are described herein. In an example, a system includes a clock management circuit adapted to receive core timing information from a core of an integrated circuit. The clock management circuit is further adapted to correlate the core timing information with a reference clock. The clock management circuit is further adapted to output frequency and time offset of the reference clock to the core timing information. The system includes an execution circuit adapted to schedule a transaction from the core at a scheduled time relative to the reference clock using the frequency and time offset. The execution circuit is further adapted to issue a command to execute the transaction at the scheduled time.

公开(公告)号：US20210064554A1

公开(公告)日：2021-03-04

申请号：US16901517

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Alexander Slota ,  James Coleman ,  Rajkumar Khandelwal ,  Anil Kumar

IPC: G06F13/12 ,  G06F12/1081 ,  G06F13/28

Abstract: System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.