公开(公告)号：US20210149736A1

公开(公告)日：2021-05-20

申请号：US17132508

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ganesh Kondapuram ,  Chetan Rawal ,  Vikram Dadwal

IPC: G06F9/50 ,  G06F15/80 ,  G06F11/30

Abstract: Methods, systems, apparatus, and articles of manufacture to extend the life of embedded processors are disclosed herein. Disclosed example apparatus include a policy selector to select a policy, based on input information. The apparatus extends an operating lifespan of a microprocessor having a plurality of cores. The apparatus also includes a cores partitioner to divide, based on the selected policy, the plurality of cores into subsets of cores, including a first subset and a second subset. A sensor monitors, based on the selected policy, at least one operational parameter of the cores, and a cores switcher switches a first core of the first subset of cores from active to inactive and to switch a second core of the second subset of cores from inactive to active based on the at least one operational parameter. The switches reduce an amount of degradation experienced by the first core and the second core.

公开(公告)号：US12288095B2

公开(公告)日：2025-04-29

申请号：US17132508

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ganesh Kondapuram ,  Chetan Rawal ,  Vikram Dadwal

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F11/30

Abstract: Methods, systems, apparatus, and articles of manufacture to extend the life of embedded processors are disclosed herein. Disclosed example apparatus include a policy selector to select a policy, based on input information. The apparatus extends an operating lifespan of a microprocessor having a plurality of cores. The apparatus also includes a cores partitioner to divide, based on the selected policy, the plurality of cores into subsets of cores, including a first subset and a second subset. A sensor monitors, based on the selected policy, at least one operational parameter of the cores, and a cores switcher switches a first core of the first subset of cores from active to inactive and to switch a second core of the second subset of cores from inactive to active based on the at least one operational parameter. The switches reduce an amount of degradation experienced by the first core and the second core.

公开(公告)号：US12301697B2

公开(公告)日：2025-05-13

申请号：US17132058

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Vikram Dadwal ,  James Coleman ,  Alexander Slota

IPC: G06F1/12 ,  G06F1/14 ,  H04L7/04

Abstract: Systems and techniques for an heterogeneous clock management solution for industrial systems are described herein. In an example, a system includes a clock management circuit adapted to receive core timing information from a core of an integrated circuit. The clock management circuit is further adapted to correlate the core timing information with a reference clock. The clock management circuit is further adapted to output frequency and time offset of the reference clock to the core timing information. The system includes an execution circuit adapted to schedule a transaction from the core at a scheduled time relative to the reference clock using the frequency and time offset. The execution circuit is further adapted to issue a command to execute the transaction at the scheduled time.