公开(公告)号：US12242721B2

公开(公告)日：2025-03-04

申请号：US17214534

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Aravinda Prasad ,  Sandeep Kumar ,  Sreenivas Subramoney ,  Andy Rudoff

IPC: G06F3/06

Abstract: Disclosed Methods, Apparatus, and articles of manufacture to profile page tables for memory management are disclosed. An example apparatus includes a processor to execute computer readable instructions to: profile a first page at a first level of a page table as not part of a target group; and in response to profiling the first page as not part of the target group, label a data page at a second level that corresponds to the first page as not part of the target group, the second level being lower than the first level.

公开(公告)号：US20210263855A1

公开(公告)日：2021-08-26

申请号：US17223113

申请日：2021-04-06

Applicant: Intel Corporation

Inventor： Andy Rudoff ,  Tiffany J. Kasanicky ,  Wei P. Chen ,  Rajat Agarwal ,  Chet R. Douglas

IPC: G06F12/0891 ,  G06F12/02

Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.

公开(公告)号：US11580029B2

公开(公告)日：2023-02-14

申请号：US17223113

申请日：2021-04-06

Applicant: Intel Corporation

Inventor： Andy Rudoff ,  Tiffany J. Kasanicky ,  Wei P. Chen ,  Rajat Agarwal ,  Chet R. Douglas

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/02

Abstract: A memory management system includes a cache invalidation logic configured to invalidate, based a cache invalidation event, cache entries within a cache memory by having each cache entry, of the cache entries within the cache memory, reference a respective dummy address from among dummy addresses within a dummy address space, wherein the cache memory is assigned to a memory, the memory has a memory address space associated therewith to provide access the memory, and each dummy address of the dummy addresses within the dummy address space is distinct from any address of the memory address space.

公开(公告)号：US20230057083A1

公开(公告)日：2023-02-23

申请号：US17818828

申请日：2022-08-10

Applicant: Intel Corporation

Inventor： Andy Rudoff

IPC: G06F12/1027 ,  G06F12/0811

Abstract: The disclosed technology provides for an improved memory tiering arrangement. In one aspect, an apparatus includes a sampling register and logic, responsive to sequential read requests, to read page data entries stored in successive locations in a TLB and provide page data from the page data entries as sequential outputs of the sampling register. In another aspect, a method includes generating a page residency list based on scanning, via a sampling register, page data entries stored in successive locations in a TLB, determining, for each page, whether the respective page is a hot page or a cold page based on the page residency list, and assigning hot pages to a first memory tier and cold pages to a second memory tier. Scanning page data entries stored in the TLB can include issuing a sequence of read requests to the sampling register sufficient to read all entries in the TLB.

公开(公告)号：US10997082B2

公开(公告)日：2021-05-04

申请号：US16451086

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Andy Rudoff ,  Tiffany J. Kasanicky ,  Wei P. Chen ,  Rajat Agarwal ,  Chet R. Douglas

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/02

Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.

公开(公告)号：US20190310944A1

公开(公告)日：2019-10-10

申请号：US16451086

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Andy Rudoff ,  Tiffany J. Kasanicky ,  Wei P. Chen ,  Rajat Agarwal ,  Chet R. Douglas

IPC: G06F12/0891 ,  G06F12/02

Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.