公开(公告)号：US11557541B2

公开(公告)日：2023-01-17

申请号：US16235879

申请日：2018-12-28

申请人： Intel Corporation

发明人： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Robert Sankman ,  Ravindranath V. Mahajan ,  Debendra Mallik ,  Ram S. Viswanath ,  Sandeep B. Sane ,  Sriram Srinivasan ,  Rajat Agarwal ,  Aravind Dasu ,  Scott Weber ,  Ravi Gutala

IPC分类号： H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

摘要： Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US20220365885A1

公开(公告)日：2022-11-17

申请号：US17872805

申请日：2022-07-25

申请人： Intel Corporation

发明人： Siddhartha Chhabra ,  Rajat Agarwal ,  Baiju Patel ,  Kirk Yap

IPC分类号： G06F12/14 ,  G06F21/78 ,  G06F21/60 ,  H04L9/32 ,  G06F21/64 ,  H04L9/14 ,  G06F21/53 ,  G06F21/85

摘要： Techniques are described for providing low-overhead cryptographic memory isolation to mitigate attack vulnerabilities in a multi-user virtualized computing environment. Memory read and memory write operations for target data, each operation initiated via an instruction associated with a particular virtual machine (VM), include the generation and/or validation of a message authentication code that is based at least on a VM-specific cryptographic key and a physical memory address of the target data. Such operations may further include transmitting the generated message authentication code via a plurality of ancillary bits incorporated within a data line that includes the target data. In the event of a validation failure, one or more error codes may be generated and provided to distinct trust domain architecture entities based on an operating mode of the associated virtual machine.

公开(公告)号：US20220114112A1

公开(公告)日：2022-04-14

申请号：US17559258

申请日：2021-12-22

申请人： Intel Corporation

发明人： Sergej Deutsch ,  Karanvir Grewal ,  David M. Durham ,  Rajat Agarwal

IPC分类号： G06F12/14 ,  G06F12/0853 ,  G06F11/10 ,  G06F11/07

摘要： A method comprises generating, for a cacheline, a first tag and a second tag, the first tag and the second tag generated as a function of user data stored and metadata in the cacheline stored in a first memory device, and a multiplication parameter derived from a secret key, storing the user data, the metadata, the first tag and the second tag in the first cacheline of the first memory device; generating, for the cacheline, a third tag and a fourth tag, the third tag and the fourth tag generated as a function of the user data stored and metadata in the cacheline stored in a second memory device, and the multiplication parameter; storing the user data, the metadata, the third tag and the fourth tag in the corresponding cache line of the second memory device; receiving, from a requesting device, a read operation directed to the cacheline; and using the first tag, the second tag, the third tag, and the fourth tag to determine whether a read error occurred during the read operation.

公开(公告)号：US11030108B2

公开(公告)日：2021-06-08

申请号：US16540163

申请日：2019-08-14

申请人： Intel Corporation

发明人： Berkin Akin ,  Rajat Agarwal ,  Jong Soo Park ,  Christopher J. Hughes ,  Chiachen Chou

IPC分类号： G06F12/08 ,  G06F12/0888 ,  G06F12/04 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0886

摘要： In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.

公开(公告)号：US10901899B2

公开(公告)日：2021-01-26

申请号：US16408870

申请日：2019-05-10

申请人： Intel Corporation

发明人： Ruchira Sasanka ,  Rajat Agarwal

IPC分类号： G06F12/0811 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/06 ,  G06F12/0897 ,  G06F12/02 ,  G06F12/1018

摘要： A processor includes a core to execute a transaction with a memory via cache; and cache controller having an index mapper circuit to: identify a physical memory address associated with the transaction and having a plurality of bits; determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value; determine a mapping function corresponding to the tag value; determine, using the mapping function, a bit-placement order; combine, based on the order, second and third set of bits to form an index; generate, using the index, a mapping from the address to a cache line index value identifying a cache line in the cache; and wherein the cache controller is further to access, using the mapping and in response to the transaction, the cache line.

公开(公告)号：US10719443B2

公开(公告)日：2020-07-21

申请号：US16363992

申请日：2019-03-25

申请人： Intel Corporation

发明人： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

IPC分类号： G11C11/406 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G11C14/00

摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US10594491B2

公开(公告)日：2020-03-17

申请号：US15816901

申请日：2017-11-17

申请人： INTEL CORPORATION

发明人： David M. Durham ,  Rajat Agarwal ,  Siddhartha Chhabra ,  Sergej Deutsch ,  Karanvir S. Grewal ,  Ioannis T. Schoinas

IPC分类号： H04L9/32 ,  G06F12/14 ,  G06F3/06 ,  G11C29/52 ,  H04L9/06 ,  G06F11/10 ,  G06F12/0886 ,  G06F21/79 ,  H04L9/08 ,  G06F21/78 ,  G11C29/44

摘要： In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.

公开(公告)号：US20190042476A1

公开(公告)日：2019-02-07

申请号：US16023576

申请日：2018-06-29

申请人： Intel Corporation

发明人： Siddhartha Chhabra ,  Rajat Agarwal ,  Baiju Patel ,  Kirk Yap

IPC分类号： G06F12/14 ,  G06F21/78 ,  G06F21/64 ,  G06F21/60 ,  H04L9/32 ,  G06F9/455

摘要： Techniques are described for providing low-overhead cryptographic memory isolation to mitigate attack vulnerabilities in a multi-user virtualized computing environment. Memory read and memory write operations for target data, each operation initiated via an instruction associated with a particular virtual machine (VM), include the generation and/or validation of a message authentication code that is based at least on a VM-specific cryptographic key and a physical memory address of the target data. Such operations may further include transmitting the generated message authentication code via a plurality of ancillary bits incorporated within a data line that includes the target data. In the event of a validation failure, one or more error codes may be generated and provided to distinct trust domain architecture entities based on an operating mode of the associated virtual machine.

公开(公告)号：US11960900B2

公开(公告)日：2024-04-16

申请号：US16729321

申请日：2019-12-28

申请人： Intel Corporation

发明人： Murugasamy K. Nachimuthu ,  Rajat Agarwal ,  Mohan J. Kumar

IPC分类号： G06F9/44 ,  G06F9/4401 ,  G06F9/445

CPC分类号： G06F9/4403 ,  G06F9/445

摘要： Technologies for fast boot-up of a compute device with error-correcting code (ECC) memory are disclosed. A basic input/output system (BIOS) of a compute device may assign memory addresses of the ECC memory to different processors on the compute device. The processors may then initialize the ECC memory in parallel by writing to the ECC memory. The processors may write to the ECC memory with direct-store operations that are immediately written to the ECC memory instead of being cached. The BIOS may continue to operation on one processor while the rest of the processors initialize the ECC memory.

公开(公告)号：US20230402077A1

公开(公告)日：2023-12-14

申请号：US18145095

申请日：2022-12-22

申请人： Intel Corporation

发明人： Sergej Deutsch ,  Christoph Dobraunig ,  Rajat Agarwal ,  David M. Durham ,  Santosh Ghosh ,  Karanvir Grewal ,  Krystian Matusiewicz

IPC分类号： G06F11/10

CPC分类号： G06F11/1044

摘要： The technology described herein includes a first plurality of bijection diffusion function circuits to diffuse data bits into diffused data bits and store the diffused data bits into a memory; an error correcting code (ECC) generation circuit to generate ECC bits for the data bits; and a second plurality of bijection diffusion function circuits to diffuse the ECC bits into diffused ECC bits and store the diffused ECC bits into the memory.