公开(公告)号：US20230317822A1

公开(公告)日：2023-10-05

申请号：US17711434

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Stephen M. CEA ,  Borna OBRADOVIC ,  Rishabh MEHANDRU ,  Jack T. KAVALIEROS

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/66553 ,  H01L29/66545 ,  H01L29/0673 ,  H01L29/0847

Abstract: Embodiments described herein may be related to transistor structures where dimpled spacers, which may also be referred to as inner spacers or offset spacers, may be formed around gates within an epitaxial structure such that the epitaxial material adjacent to the dimpled spacer is uniform and/or defect free. In embodiments, forming the dimpled spacers occurs after epitaxial growth. Other embodiments may be described and/or claimed.