-
公开(公告)号:US20210117360A1
公开(公告)日:2021-04-22
申请号:US17134361
申请日:2020-12-26
Applicant: Intel Corporation
Inventor: Patrick G. KUTCH , Andrey CHILIKIN , Niall D. MCDONNELL , Brian A. KEATING , Naveen LAKKAKULA , Ilango S. GANGA , Venkidesh KRISHNA IYER , Patrick FLEMING , Lokpraveen MOSUR
Abstract: Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.
-
公开(公告)号:US20190075063A1
公开(公告)日:2019-03-07
申请号:US16177262
申请日:2018-10-31
Applicant: Intel Corporation
Inventor: Niall D. MCDONNELL , Bruce RICHARDSON , John MANGAN , Harry VAN HAAREN , Ciara LOFTUS , Brian A. KEATING
IPC: H04L12/931 , H04L12/861 , G06F9/54 , G06F13/10
Abstract: Examples include a method of switching a packet by a virtual switch by receiving a system call to transmit a packet from a first application running in a first container on a first core, determining a destination for the packet, obtaining a buffer in an application memory space of the destination, copying the packet to the destination application memory space, and writing an entry for the packet to a queue assigned to the destination, the destination queue being in a queue manager. The packet may then be obtained by an entity at the destination.
-