公开(公告)号：US20190213330A1

公开(公告)日：2019-07-11

申请号：US16354258

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： CHAIM SHEN-ORR ,  BARUCH CHAIKIN ,  AHMAD YASIN ,  REUVEN ELBAUM

IPC: G06F21/56 ,  G06F12/1027

Abstract: The present disclosure is directed to systems and methods of detecting a side-channel attack detecting a translation lookaside buffer (TLB) miss on a virtual address lookup caused by the speculative execution of an instruction and determining that the physical memory address associated with the virtual address lookup contains a privileged object or a secret object. Range register circuitry determines whether the physical memory address is located in an address range containing privileged objects or secret objects. Performance monitoring counter circuitry receives information indicative of the TLB miss and information indicative that the physical memory address contains a privileged object or a secret object. The PMC circuitry generates an interrupt in response to receipt of information indicative of the TLB miss and information indicative that the physical memory address contains a privileged object or a secret object. The PMC circuitry causes the storage of information associated with the speculatively executed instruction causing the virtual address lookup.