公开(公告)号：US20180189161A1

公开(公告)日：2018-07-05

申请号：US15396293

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： AHMAD YASIN ,  MOSHE COHEN ,  JACOB JACK DOWECK

IPC: G06F11/30 ,  G06F9/38

CPC classification number: G06F11/3024 ,  G06F9/46

Abstract: An apparatus and method are described for generating performance metrics of a processor. For example, one embodiment of a processor comprises: one or more simultaneous multithreading cores to simultaneously execute multiple instruction threads; a plurality of performance monitor counters, each to maintain a count of events occurring as a result of the execution of the multiple instruction threads; and a performance monitor unit to generate a plurality of performance metric values using the event counts stored in the performance monitor counters and in response to receipt of a request from software for the performance metric values.

公开(公告)号：US20220012144A1

公开(公告)日：2022-01-13

申请号：US17242018

申请日：2021-04-27

Applicant: Intel Corporation

Inventor： AHMAD YASIN

IPC: G06F11/30 ,  G06F11/34

Abstract: An apparatus and method are described for a multithreaded-aware performance monitor of a processor. For example, one embodiment of a processor comprises: one or more simultaneous multithreading cores to simultaneously execute multiple instruction threads; a plurality of performance monitor counters, each performance monitor counter to count baseline events during processing of the multiple instruction threads; and a performance monitor circuit to determine whether multiple threads are concurrently generating the same baseline event and, if so, then the performance monitor circuit to distribute the count of the baseline event for only one of the multiple threads in each processor cycle for which the multiple threads are active and the baseline event applies to.

公开(公告)号：US20180189160A1

公开(公告)日：2018-07-05

申请号：US15395903

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： AHMAD YASIN

IPC: G06F11/30 ,  G06F9/38 ,  G06F11/34

CPC classification number: G06F11/3024 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/348 ,  G06F2201/88

Abstract: An apparatus and method are described for a multithreaded-aware performance monitor of a processor. For example, one embodiment of a processor comprises: one or more simultaneous multithreading cores to simultaneously execute multiple instruction threads; a plurality of performance monitor counters, each performance monitor counter to count baseline events during processing of the multiple instruction threads; and a performance monitor circuit to determine whether multiple threads are concurrently generating the same baseline event and, if so, then the performance monitor circuit to distribute the count of the baseline event for only one of the multiple threads in each processor cycle for which the multiple threads are active and the baseline event applies to.

公开(公告)号：US20220308882A1

公开(公告)日：2022-09-29

申请号：US17214823

申请日：2021-03-27

Applicant: Intel Corporation

Inventor： JONATHAN COMBS ,  MICHAEL CHYNOWETH ,  BEEMAN STRONG ,  CHARLIE HEWETT ,  PATRICK KONSOR ,  VIDISHA CHIRRA ,  ASAVARI PARANJAPE ,  AHMAD YASIN

IPC: G06F9/38 ,  G06F12/0802 ,  G06F11/30 ,  G06F11/34

Abstract: Systems, methods, and apparatuses relating to circuitry to implement precise last branch record event logging in a processor are described. In one embodiment, a hardware processor core includes an execution circuit to execute instructions, a retirement circuit to retire executed instructions, a status register, and a last branch record circuit to, in response to retirement by the retirement circuit of a first taken branch instruction, start a cycle timer and a performance monitoring event counter, and in response to retirement by the retirement circuit of a second taken branch instruction, that is a next taken branch instruction in program order after the first taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a first entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.

公开(公告)号：US20210208990A1

公开(公告)日：2021-07-08

申请号：US17125694

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： AHMAD YASIN ,  MOSHE COHEN ,  JACOB JACK DOWECK

IPC: G06F11/30 ,  G06F9/46

Abstract: An apparatus and method are described for generating performance metrics of a processor. For example, one embodiment of a processor comprises: one or more simultaneous multithreading cores to simultaneously execute multiple instruction threads; a plurality of performance monitor counters, each to maintain a count of events occurring as a result of the execution of the multiple instruction threads; and a performance monitor unit to generate a plurality of performance metric values using the event counts stored in the performance monitor counters and in response to receipt of a request from software for the performance metric values.

公开(公告)号：US20190213330A1

公开(公告)日：2019-07-11

申请号：US16354258

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： CHAIM SHEN-ORR ,  BARUCH CHAIKIN ,  AHMAD YASIN ,  REUVEN ELBAUM

IPC: G06F21/56 ,  G06F12/1027

Abstract: The present disclosure is directed to systems and methods of detecting a side-channel attack detecting a translation lookaside buffer (TLB) miss on a virtual address lookup caused by the speculative execution of an instruction and determining that the physical memory address associated with the virtual address lookup contains a privileged object or a secret object. Range register circuitry determines whether the physical memory address is located in an address range containing privileged objects or secret objects. Performance monitoring counter circuitry receives information indicative of the TLB miss and information indicative that the physical memory address contains a privileged object or a secret object. The PMC circuitry generates an interrupt in response to receipt of information indicative of the TLB miss and information indicative that the physical memory address contains a privileged object or a secret object. The PMC circuitry causes the storage of information associated with the speculatively executed instruction causing the virtual address lookup.

公开(公告)号：US20170262290A1

公开(公告)日：2017-09-14

申请号：US15438679

申请日：2017-02-21

Applicant: Intel Corporation

Inventor： AHMAD YASIN ,  PEGGY J. IRELAN ,  OFER LEVY ,  EMILE ZIEDAN ,  GRANT G. ZHOU

IPC: G06F9/38 ,  G06F11/34

CPC classification number: G06F9/3861 ,  G06F9/3857 ,  G06F11/3466 ,  G06F11/3476 ,  G06F2201/86 ,  G06F2201/88

Abstract: Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.