METHODS AND DEVICES FOR SELF-INTERFERENCE CANCELATION

    公开(公告)号:US20190229884A1

    公开(公告)日:2019-07-25

    申请号:US16327386

    申请日:2016-09-29

    Abstract: A communication circuit arrangement includes a first kernel dimension filter circuit configured to apply a first kernel dimension filter to a first input signal to estimate a first kernel dimension interference signal from a first amplifier, a second kernel dimension filter circuit configured to apply a second kernel dimension filter to a second input signal to estimate a second kernel dimension interference signal from a second amplifier, a joint delay tap dimension filter configured to apply a joint delay tap dimension filter to a combination of the first kernel dimension interference signal and the second kernel dimension interference signal to obtain an estimated joint interference signal, and a cancelation circuit configured to remove the estimated joint interference signal from a received signal to obtain a clean signal.

    HYBRID SCHEDULING AND LATCH-BASED PIPELINES FOR LOW-DENSITY PARITY-CHECK DECODING

    公开(公告)号:US20180351575A1

    公开(公告)日:2018-12-06

    申请号:US15778239

    申请日:2015-12-24

    Abstract: A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.

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