公开(公告)号：US20190052530A1

公开(公告)日：2019-02-14

申请号：US16160176

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Mohammad Abdul AWAL ,  Jasvinder SINGH ,  Reshma PATTAN ,  David HUNT ,  Declan DOHERTY ,  Chris MACNAMARA

IPC: H04L12/24 ,  H04L12/26 ,  H04L12/861

Abstract: Examples include techniques for monitoring a data packet transfer rate at an interface queue, and based at least in part on a comparison of the data packet transfer rate to a threshold, assigning the interface queue from a core of a first class to a core of a second class or assigning the interface queue from a core of the second class to a core of the first class.

公开(公告)号：US20230198912A1

公开(公告)日：2023-06-22

申请号：US17553543

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Niall MCDONNELL ,  Pravin PATHAK ,  Rahul SHAH ,  Declan DOHERTY

IPC: H04L47/34 ,  H04L47/2441 ,  H04L47/27

CPC classification number: H04L47/34 ,  H04L47/2441 ,  H04L47/27 ,  H04L63/18

Abstract: Methods and apparatus to assign and check anti-replay sequence numbers. In one embodiment, a method includes assigning, by circuitry, sequence numbers to packets of traffic flows, wherein a first sequence number is assigned to a first packet based on a determination that the first packet is within a first traffic flow mapped to a first secure channel, and wherein the first sequence number is within a set of sequence numbers allocated to the first secure channel and maintained by the circuitry. The method continues with allocating the packets of traffic flows to be processed among a plurality of processor cores and processing the packets of traffic flows by the plurality of processor cores.

公开(公告)号：US20210014324A1

公开(公告)日：2021-01-14

申请号：US17031659

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Andrey CHILIKIN ,  Tomasz KANTECKI ,  Chris MACNAMARA ,  John J. BROWNE ,  Declan DOHERTY ,  Niall POWER

IPC: H04L29/08 ,  H04L12/24 ,  H04L12/26 ,  G06F12/0862 ,  G06F1/28

Abstract: Examples described herein relate to a network interface apparatus that includes an interface; circuitry to determine whether to store content of a received packet into a cache or into a memory, at least during a configuration of the network interface to store content directly into the cache, based at least in part on a fill level of a region of the cache allocated to receive copies of packet content directly from the network interface; and circuitry to store content of the received packet into the cache or the memory based on the determination, wherein the cache is external to the network interface. In some examples, the network interface is to determine to store content of the received packet into the memory based at least in part on a fill level of the region of the cache being identified as full or determine to store content of the received packet into the cache based at least in part on a fill level of the region of the cache being identified as not filled. In some examples, the network interface is to indicate a complexity level of content of the received packet to cause adjustment of a power usage level of a processor that is to process the content of the received packet.