公开(公告)号：US20230401109A1

公开(公告)日：2023-12-14

申请号：US18237860

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Niall D. MCDONNELL ,  Ambalavanar ARULAMBALAM ,  Te Khac MA ,  Surekha PERI ,  Pravin PATHAK ,  James CLEE ,  An YAN ,  Steven POLLOCK ,  Bruce RICHARDSON ,  Vijaya Bhaskar KOMMINENI ,  Abhinandan GUJJAR

IPC: G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/5038

Abstract: Examples described herein relate to a load balancer that is configured to selectively perform ordering of requests from the one or more cores, allocate the requests into queue elements prior to allocation to one or more receiver cores of the one or more cores to process the requests, and perform two or more operations of: adjust a number of queues associated with a core of the one or more cores by changing a number of consumer queues (CQs) allocated to a single domain, adjust a number of target cores in a group of target cores to be load balanced, and order memory space writes from multiple caching agents (CAs).

公开(公告)号：US20220107838A1

公开(公告)日：2022-04-07

申请号：US17644117

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Niall MCDONNELL ,  Bruce RICHARDSON ,  Rahul SHAH ,  Pravin PATHAK ,  Rashmi SHETTY

IPC: G06F9/48

Abstract: Examples relate to an apparatus, device, method, and computer program for processing a sequence of units of data, and of a computer program comprising such an apparatus or device. The apparatus comprises processing circuitry configured to obtain the sequence of units of data, obtain tokens indicating a readiness of a plurality of worker threads being executed on the processing circuitry, and process sub-sequences of the sequence of units of data by selecting, by a queue management circuitry of the processing circuitry, a worker thread from the plurality of worker threads based on the obtained tokens indicating the readiness, providing, by the queue management circuitry, a lock to a queue associated with the worker thread, the lock being associated with a resource comprising a sub-sequence of the sequence of units of data, obtaining, by the queue management circuitry, the lock from the worker thread after the worker thread has at least partially processed the sub-sequence of units of data stored in the resource, and proceeding with the next sub-sequence after the lock has been obtained.

公开(公告)号：US20190253357A1

公开(公告)日：2019-08-15

申请号：US16160096

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Pravin PATHAK ,  Sundar VEDANTHAM ,  David SONNIER

IPC: H04L12/803 ,  H04L12/863 ,  H04L12/851

CPC classification number: H04L47/125 ,  H04L47/2441 ,  H04L47/6215 ,  H04L47/622 ,  H04L47/624 ,  H04L47/6255

Abstract: A computing platform includes a classifier to classify a packet and assign a processing load weight to the packet based at least in part on the packet classification; and a load balancer coupled to the classifier to compute a total processing load weight of a queue of a packet processing system and assign the packet to a queue with a lowest total processing load weight.

公开(公告)号：US20230198912A1

公开(公告)日：2023-06-22

申请号：US17553543

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Niall MCDONNELL ,  Pravin PATHAK ,  Rahul SHAH ,  Declan DOHERTY

IPC: H04L47/34 ,  H04L47/2441 ,  H04L47/27

CPC classification number: H04L47/34 ,  H04L47/2441 ,  H04L47/27 ,  H04L63/18

Abstract: Methods and apparatus to assign and check anti-replay sequence numbers. In one embodiment, a method includes assigning, by circuitry, sequence numbers to packets of traffic flows, wherein a first sequence number is assigned to a first packet based on a determination that the first packet is within a first traffic flow mapped to a first secure channel, and wherein the first sequence number is within a set of sequence numbers allocated to the first secure channel and maintained by the circuitry. The method continues with allocating the packets of traffic flows to be processed among a plurality of processor cores and processing the packets of traffic flows by the plurality of processor cores.

公开(公告)号：US20210049285A1

公开(公告)日：2021-02-18

申请号：US17083149

申请日：2020-10-28

Applicant: Intel Corporation

Inventor： Sundar VEDANTHAM ,  Bin LIN ,  Pravin PATHAK ,  Ximing CHEN ,  Chris MACNAMARA

IPC: G06F21/60 ,  G06F16/27

Abstract: Examples described herein relate to a manner of provide a time of life of data. In some examples, data and control parameters are received from a data source. The data can be encrypted and stored. In addition, at least a portion of the control parameters can be stored into a distributed ledger. In some examples, the portion of the control parameters include an indicator of expiration time of the data. In some examples, a data header for the data is generated, where the data header includes an indication that the data is subject to a limited life span and a data identifier. The data header can be accessed with a request to access the encrypted data. In some examples, a request to determine if the data is valid and accessible is provided to a node of the distributed ledger and an indication of whether the data is valid and accessible is received from a node in the distributed ledger.