公开(公告)号：US20240028815A1

公开(公告)日：2024-01-25

申请号：US18375299

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Xiangyong Wang ,  David Kehlet ,  Diana Cristina Ojeda Aristizabal ,  Ian Kuon ,  Mehmet Avci

IPC: G06F30/398

CPC classification number: G06F30/398 ,  G06F2119/12

Abstract: Integrated circuit devices, methods, and circuitry are provided for performing timing analysis for chip-to-chip connections between integrated circuits in a multichip package. A system may include an integrated circuit package and a computing system. The integrated circuit package may have a first integrated circuit connected to a second integrated circuit via a chip-to-chip connection. The chip-to-chip connection may also be connected to a package ball. The computing system may perform timing analysis on a circuit design for the first integrated circuit with respect the chip-to-chip connection based on user-specified parasitic data relating to the connection to the package ball.

公开(公告)号：US20220116042A1

公开(公告)日：2022-04-14

申请号：US17559831

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Atul Maheshwari ,  Mahesh Iyer ,  Mahesh K. Kumashikar ,  Ian Kuon ,  Yuet Li ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC: H03K19/177

Abstract: Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.

公开(公告)号：US12273107B2

公开(公告)日：2025-04-08

申请号：US17559831

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Atul Maheshwari ,  Mahesh Iyer ,  Mahesh K. Kumashikar ,  Ian Kuon ,  Yuet Li ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC: H03K19/177 ,  G06F30/34

Abstract: Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.