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    Techniques For Clock Signal Transmission In Integrated Circuits And Interposers
    1.
    发明申请
    Techniques For Clock Signal Transmission In Integrated Circuits And Interposers 有权

    公开(公告)号：US20230049681A1

    公开(公告)日：2023-02-16

    申请号：US17973428

    申请日：2022-10-25

    申请人： Intel Corporation

    发明人： Jeffrey Chromczak ,  Chooi Pei Lim ,  Lai Guan Tang ,  Chee Hak Teh ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu

    IPC分类号： G06F1/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538

    摘要： An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.

    PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION
    4.
    发明申请
    PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION 审中-公开

    公开(公告)号：US20200186149A1

    公开(公告)日：2020-06-11

    申请号：US16788760

    申请日：2020-02-12

    申请人： Intel Corporation

    发明人： Dheeraj Subbareddy ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

    IPC分类号： H03K19/1776 ,  H01L25/18 ,  H01L23/367

    摘要： A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

    Dual in-line memory module (DIMM) programmable accelerator card
    5.
    发明授权
    Dual in-line memory module (DIMM) programmable accelerator card 有权

    公开(公告)号：US10649927B2

    公开(公告)日：2020-05-12

    申请号：US16211868

    申请日：2018-12-06

    申请人： Intel Corporation

    发明人： Sharath Raghava ,  Dheeraj Subbareddy ,  Kavitha Prasad ,  Ankireddy Nalamalpu ,  Harsha Gupta

    IPC分类号： G06F13/38 ,  G06F13/16 ,  G06F13/12 ,  G06F13/42

    摘要： A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.

    Interface Bus for Inter-Die Communication in a Multi-Chip Package Over High Density Interconnects
    7.
    发明申请
    Interface Bus for Inter-Die Communication in a Multi-Chip Package Over High Density Interconnects 审中-公开

    公开(公告)号：US20190042505A1

    公开(公告)日：2019-02-07

    申请号：US16023724

    申请日：2018-06-29

    申请人： Intel Corporation

    发明人： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  MD Altaf Hossain

    IPC分类号： G06F13/38 ,  G06F13/42 ,  H01L23/00 ,  H01L25/065

    摘要： An IC includes first, second, and third IOs, and a multiplexer that includes first and second inputs, and an output. The IC includes first and second transmitters respectively having an output coupled to the first IO and an output coupled to the second IO. A clock generator is coupled between the output and an input of the first transmitter and between the output and an input of the second transmitter. The first input may receive a clock signal generated by the first clock generator and the second clock input is coupled to the third IO and may receive a clock signal via the third IO element from another IC. An IC includes a programmable fabric, k*n wires coupled to and extending from the fabric, n TDMs, and n IO blocks. Each TDM includes k inputs coupled to k wires and an output coupled to one of the IO blocks.

    SEGMENTED ROW REPAIR FOR PROGRAMMABLE LOGIC DEVICES
    10.
    发明申请
    SEGMENTED ROW REPAIR FOR PROGRAMMABLE LOGIC DEVICES 有权

    公开(公告)号：US20220113350A1

    公开(公告)日：2022-04-14

    申请号：US17559322

    申请日：2021-12-22

    申请人： Intel Corporation

    发明人： Dheeraj Subbareddy ,  Arun Jangity ,  Ramya Yeluri ,  Mahesh K. Kumashikar ,  Atul Maheshwari ,  Ankireddy Nalamalpu

    IPC分类号： G01R31/3177

    摘要： Systems or methods of the present disclosure may provide a programmable logic device including multiple logic array blocks each having multiple programmable elements. The multiple logic array blocks are arranged in multiple rows that are segmented into multiple segments. The programmable logic device also includes repair circuitry disposed between the multiple segments. The repair circuitry remaps logic within a first segment of the multiple segments when a first logic array block of the multiple logic array blocks has failed. Moreover, the first segment includes the first logic array block.