公开(公告)号：US11652067B2

公开(公告)日：2023-05-16

申请号：US16465126

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Radek P. Chalupa ,  Flavio Griggio ,  Inane Meric ,  Jiun-Chan Yang

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/7684 ,  H01L23/5226

Abstract: Methods/structures of forming substrate tap structures are described. Those methods/structures may include forming a plurality of conductive interconnect structures on an epitaxial layer disposed on a substrate, wherein individual ones of the plurality of conductive interconnect structures are adjacent each other, forming a portion of a seed layer on at least one of the plurality of conductive interconnect structures, and forming a conductive trace on the seed layer.