公开(公告)号：US11869894B2

公开(公告)日：2024-01-09

申请号：US17864264

申请日：2022-07-13

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Anh Phan ,  Patrick Morrow ,  Willy Rachmady ,  Gilbert Dewey ,  Jessica M. Torres ,  Kimin Jun ,  Tristan A. Tronic ,  Christopher J. Jezewski ,  Hui Jae Yoo ,  Robert S. Chau ,  Chi-Hwa Tsang

IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H10B61/00 ,  H10B63/00

CPC分类号： H01L27/1207 ,  H01L21/02532 ,  H01L21/28568 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H10B61/22 ,  H10B63/30

摘要： A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

公开(公告)号：US20230395717A1

公开(公告)日：2023-12-07

申请号：US17833045

申请日：2022-06-06

申请人： Intel Corporation

发明人： Willy Rachmady ,  Nitesh Kumar ,  Jami A. Wiedemer ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Mauro J. Kobrinsky ,  Patrick Morrow ,  Rohit Galatage ,  David N. Goldstein ,  Christopher J. Jezewski

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/45 ,  H01L27/092

CPC分类号： H01L29/7845 ,  H01L29/42392 ,  H01L29/0665 ,  H01L29/45 ,  H01L27/092

摘要： An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device. The first device includes (i) a first source region, and a first source contact including a first conductive material, (ii) a first drain region, and a first drain contact including the first conductive material, and (iii) a first body laterally between the first source region and the first drain region. The second device includes (i) a second source region, and a second source contact including a second conductive material, (ii) a second drain region, and a second drain contact including the second conductive material, and (iii) a second body laterally between the second source region and the second drain region. The first and second conductive materials are compositionally different. The first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.

公开(公告)号：US20230197836A1

公开(公告)日：2023-06-22

申请号：US17557128

申请日：2021-12-21

申请人： Intel Corporation

发明人： Carl Hugo Naylor ,  Christopher J. Jezewski ,  Jeffery D. Bielefeld ,  Jiun-Ruey Chen ,  Ramanan V. CHEBIAM ,  Mauro J. Kobrinsky ,  Matthew V. Metz ,  Scott B. Clendenning ,  Sudurat Lee ,  Kevin P. O'Brien ,  Kirby Kurtis Maxey ,  Ashish Verma Penumatcha ,  Chelsey Jane Dorow ,  Uygar E. Avci

IPC分类号： H01L29/76 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/7606 ,  H01L29/0665 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02568 ,  H01L29/401 ,  H01L29/66969

摘要： Described herein are integrated circuit devices with conductive regions formed from MX or MAX materials. MAX materials are layered, hexagonal carbides and nitrides that include an early transition metal (M) and an A group element (A). MX materials remove the A group element. MAX and MX materials are highly conductive, and their two-dimensional layer structure allows very thin layers to be formed. MAX or MX materials can be used to form several conductive elements of IC circuits, including contacts, interconnects, or liners or barrier regions for contacts or interconnects.

公开(公告)号：US11557536B2

公开(公告)日：2023-01-17

申请号：US16649901

申请日：2017-12-27

申请人： Intel Corporation

发明人： Kevin Lin ,  Christopher J. Jezewski ,  Manish Chandhok

IPC分类号： H01L23/522 ,  H01L21/768

摘要： Integrated circuit (IC) interconnect lines having improved electromigration resistance. Multi-patterning may be employed to define a first mask pattern. The first mask pattern may be backfilled and further patterned based on a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of material underlying openings defined in the second mask layer that exceed the threshold are removed. First trenches in an underlying dielectric material layer may be etched based on a union of the remainder of the first mask layer and the partially occluded second mask layer. The first trenches may then be backfilled with a first conductive material to form first line segments. Additional trenches in the underlayer may then be etched and backfilled with a second conductive material to form second line segments that are coupled together by the first line segments.

公开(公告)号：US11522059B2

公开(公告)日：2022-12-06

申请号：US15899590

申请日：2018-02-20

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert W. Dewey ,  Van H. Le ,  Lawrence D. Wong ,  Christopher J. Jezewski

IPC分类号： H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/45 ,  H01L23/29 ,  H01L29/24 ,  H01L29/22

摘要： Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.

公开(公告)号：US11462684B2

公开(公告)日：2022-10-04

申请号：US16226198

申请日：2018-12-19

申请人： Intel Corporation

发明人： Albert Chen ,  Nathan Strutt ,  Oleg Golonzka ,  Pedro Quintero ,  Christopher J. Jezewski ,  Elijah V. Karpov

IPC分类号： H01L45/00

摘要： An RRAM device is disclosed. The RRAM device includes a bottom electrode, a high-k material on the bottom electrode, a top electrode, a top contact on the top electrode and an encapsulating layer of Al2O3. The encapsulating layer encapsulates the bottom electrode, the high-k material, the top electrode and the top contact.

公开(公告)号：US20220084942A1

公开(公告)日：2022-03-17

申请号：US17017735

申请日：2020-09-11

申请人： Intel Corporation

发明人： Elijah V. Karpov ,  Christopher J. Jezewski ,  Manish Chandhok ,  Nafees A. Kabir ,  Matthew V. Metz

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768

摘要： Methods for fabricating metallization stacks with one or more self-aligned staggered metal lines, and related semiconductor devices, are disclosed. Methods and devices are based on providing a spacer material conformal to bottom metal lines of a first layer of a metallization stack. By carefully designing parameters of the deposition process, the spacer material may be deposited in such a manner that, for each pair of adjacent bottom metal lines of the first layer, an opening in the spacer material is formed in a layer above the bottom metal lines (i.e., in the second layer of the metallization stack), the opening being substantially equidistant to the adjacent bottom metal lines of the first layer. Top metal lines are formed by filling the openings with an electrically conductive material, resulting in the top metal lines being self-aligned and staggered with respect to the bottom metal lines.

公开(公告)号：US12033896B2

公开(公告)日：2024-07-09

申请号：US17863292

申请日：2022-07-12

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Christopher J. Jezewski ,  Willy Rachmady ,  Rishabh Mehandru ,  Gilbert Dewey ,  Anh Phan

IPC分类号： H01L21/8234 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L29/7842 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/785

摘要： In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.

公开(公告)号：US20230197823A1

公开(公告)日：2023-06-22

申请号：US17559332

申请日：2021-12-22

申请人： Intel Corporation

发明人： Christopher J. Jezewski ,  Matthew V. Metz

IPC分类号： H01L29/45 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/423 ,  H01L21/285 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/45 ,  H01L21/823871 ,  H01L21/0259 ,  H01L29/42392 ,  H01L21/28568 ,  H01L21/823807 ,  H01L21/32131 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/66742 ,  H01L29/78696

摘要： Complementary metal-oxide-semiconductor (CMOS) devices and methods related to selective metal contacts to n-type and p-type source and drain semiconductors are discussed. A p-type metal is deposited on n- and p-type source/drains. The p-type metal is selectively removed from the n-type source/drains but remains on dielectric materials adjacent the n-type source/drains. An n-type metal is deposited on the n-type source/drains while the remaining p-type metal seals the dielectric materials to protect the n-type metal from contamination. The n-type metal is then sealed using another p-type metal. A contact fill material contacts the resultant source and drain contact stacks.

公开(公告)号：US11652067B2

公开(公告)日：2023-05-16

申请号：US16465126

申请日：2016-12-28

申请人： Intel Corporation

发明人： Christopher J. Jezewski ,  Radek P. Chalupa ,  Flavio Griggio ,  Inane Meric ,  Jiun-Chan Yang

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/562 ,  H01L21/7684 ,  H01L23/5226

摘要： Methods/structures of forming substrate tap structures are described. Those methods/structures may include forming a plurality of conductive interconnect structures on an epitaxial layer disposed on a substrate, wherein individual ones of the plurality of conductive interconnect structures are adjacent each other, forming a portion of a seed layer on at least one of the plurality of conductive interconnect structures, and forming a conductive trace on the seed layer.