公开(公告)号：US20180189232A1

公开(公告)日：2018-07-05

申请号：US15396522

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Rahul PAL ,  Ishwar AGARWAL

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F15/80 ,  G06F15/17381

Abstract: A hetero-mesh architecture is provided to enable varying densities of tile in a multi-core processor. The hetero-mesh architecture includes areas with different tile sizes and wire densities operating and different bandwidths. A split merge switch is utilized between the different parts of the hetero-mesh to enable the sending of packets from tiles in one area of the hetero-mesh to another area of the hetero-mesh while employing a single end to end communication protocol.