公开(公告)号：US20230236995A1

公开(公告)日：2023-07-27

申请号：US18127324

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Ramkumar JAYARAMAN ,  Robert BLANKENSHIP ,  Yojan CHITKARA ,  Rahul PAL

IPC: G06F13/16 ,  G06F12/084

CPC classification number: G06F13/1668 ,  G06F12/084 ,  G06F2212/603

Abstract: Techniques to shared system memory across nodes in a system. Circuitry is arranged to provide a mechanism to share a memory region of a memory maintained at a first host CPU at a first node across multiple other host CPUs at multiple other nodes using various links and protocols described in one or more revisions of the Compute Express Link (CXL) specification.

公开(公告)号：US20220222194A1

公开(公告)日：2022-07-14

申请号：US17711986

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Neelam CHANDWANI ,  Shridhar BENDI ,  Rajesh VIVEKANANDHAM ,  Rahul PAL ,  Eric J. DAHLEN ,  Antonio J. HASBUN MARIN ,  Chung-Chi WANG ,  Qian LI ,  Hosein NIKOPOUR ,  Sravanthi KOTA VENKATA ,  Rajesh POORNACHANDRAN ,  Udayan MUKHERJEE

IPC: G06F13/40 ,  G06F13/16

Abstract: Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.

公开(公告)号：US20180189232A1

公开(公告)日：2018-07-05

申请号：US15396522

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Rahul PAL ,  Ishwar AGARWAL

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F15/80 ,  G06F15/17381

Abstract: A hetero-mesh architecture is provided to enable varying densities of tile in a multi-core processor. The hetero-mesh architecture includes areas with different tile sizes and wire densities operating and different bandwidths. A split merge switch is utilized between the different parts of the hetero-mesh to enable the sending of packets from tiles in one area of the hetero-mesh to another area of the hetero-mesh while employing a single end to end communication protocol.