公开(公告)号：US20180095889A1

公开(公告)日：2018-04-05

申请号：US15283318

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Xueyan Wang ,  Wenjuan Mao ,  Qiang Li ,  John V. Lovelace ,  James R. Goffena

IPC: G06F12/0895 ,  G06F12/0875 ,  G06F12/10 ,  G06F9/445

CPC classification number: G06F9/44505 ,  G06F12/0875 ,  G06F13/00 ,  G06F2212/452

Abstract: Technologies for control and status register (CSR) access include a computing device that starts a firmware initialization phase. The firmware accesses a CSR at an abstract CSR address. The computing device determines whether an upper part of the CSR address matches a cached upper part of a previously accessed CSR address. If the upper parts do not match, the computing device converts the CSR address into a physical address and caches the upper part of the CSR address and the upper part of the physical address. If the upper parts match, the computing device combines a cached upper part of a previously accessed physical address with an offset of the CSR address. The upper part may include 20 bits and the lower part may include 12 bits. The physical address may be a PCIe address of the CSR added with an MMCFG base address. Other embodiments are described and claimed.

公开(公告)号：US10289431B2

公开(公告)日：2019-05-14

申请号：US15283318

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Xueyan Wang ,  Wenjuan Mao ,  Qiang Li ,  John V. Lovelace ,  James R. Goffena

IPC: G06F9/445 ,  G06F13/00 ,  G06F12/0875

Abstract: Technologies for control and status register (CSR) access include a computing device that starts a firmware initialization phase. The firmware accesses a CSR at an abstract CSR address. The computing device determines whether an upper part of the CSR address matches a cached upper part of a previously accessed CSR address. If the upper parts do not match, the computing device converts the CSR address into a physical address and caches the upper part of the CSR address and the upper part of the physical address. If the upper parts match, the computing device combines a cached upper part of a previously accessed physical address with an offset of the CSR address. The upper part may include 20 bits and the lower part may include 12 bits. The physical address may be a PCIe address of the CSR added with an MMCFG base address. Other embodiments are described and claimed.