公开(公告)号：US12130744B2

公开(公告)日：2024-10-29

申请号：US17672116

申请日：2022-02-15

Applicant: Mobileye Vision Technologies Ltd.

Inventor： Yosef Kreinin ,  Yosi Arbeli ,  Gil Israel Dogon

IPC: G06F9/30 ,  G06F7/00 ,  G06F9/345 ,  G06F9/38 ,  G06F9/52 ,  G06F11/10 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F15/78 ,  G06F15/80 ,  G06T1/20 ,  G06F12/0811

CPC classification number: G06F12/0875 ,  G06F7/00 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/345 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3865 ,  G06F9/3891 ,  G06F9/526 ,  G06F11/1008 ,  G06F12/084 ,  G06F12/0842 ,  G06F15/7867 ,  G06F15/80 ,  G06T1/20 ,  G06F12/0811 ,  G06F2212/452 ,  G06F2212/62

Abstract: A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.

公开(公告)号：US12118360B2

公开(公告)日：2024-10-15

申请号：US18093643

申请日：2023-01-05

Applicant: Ventana Micro Systems Inc.

Inventor： John G. Favor ,  Michael N. Michael

IPC: G06F9/38 ,  G06F12/0875

CPC classification number: G06F9/3806 ,  G06F12/0875 ,  G06F2212/452

Abstract: A microprocessor that includes a prediction unit (PRU) comprising a branch target buffer (BTB). Each BTB entry is associated with a fetch block (FBlk) (sequential set of instructions starting at a fetch address (FA)) having a length (no longer than a predetermined maximum length) and termination type. The termination type is from a list comprising: a sequential termination type indicating that a FA of a next FBlk in program order is sequential to a last instruction of the FBlk, and one or more non-sequential termination types. The PRU uses the FA of a current FBlk to generate a current BTB lookup value, looks up the current BTB lookup value, and in response to a miss, predicts the current FBlk has the predetermined maximum length and sequential termination type. An instruction fetch unit uses the current FA and predicted predetermined maximum length to fetch the current FBlk from an instruction cache.

公开(公告)号：US20240330203A1

公开(公告)日：2024-10-03

申请号：US18739768

申请日：2024-06-11

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Timothy David Anderson

IPC: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: Devices and methods are provided for performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers. In an example, a device includes a processor that includes a multiply circuit. The multiply circuit is configured to multiply floating point numbers in response to a floating point multiply instruction, and is further configured to determine values of implied bits of mantissas of the floating point numbers, and multiply the mantissas in parallel with the determining operation.

公开(公告)号：US12105635B2

公开(公告)日：2024-10-01

申请号：US17384858

申请日：2021-07-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Mujibur Rahman ,  Dheera Balasubramanian Samudrala ,  Peter Richard Dent ,  Duc Quang Bui

IPC: G06F9/30 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1045 ,  G06F17/16 ,  H03H17/06 ,  G06F15/78

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

公开(公告)号：US20240302958A1

公开(公告)日：2024-09-12

申请号：US18657466

申请日：2024-05-07

Applicant: Micron Technology, Inc.

Inventor： Horia C. Simionescu ,  Chung Kuang Chin

IPC: G06F3/06 ,  G06F12/0802 ,  G06F12/10 ,  G06F12/123

CPC classification number: G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G06F12/10 ,  G06F12/124 ,  G06F12/0802 ,  G06F2212/452

Abstract: Managed units (MUs) of data can be stored on a memory device according to a slice-based layout. A slice of the slice-based layout can include a plurality of stripes, each of the stripes including respective partitions and respective MUs of data. A subset of the stripes each include a quantity of partitions and a first quantity of MUs of data. Another subset of the stripes each include a lesser quantity of partitions and a lesser quantity of MUs of data.

公开(公告)号：US12079470B2

公开(公告)日：2024-09-03

申请号：US17379345

申请日：2021-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Matthew Pierson

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/14

CPC classification number: G06F3/0604 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/3802 ,  G06F9/383 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/14 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/60

Abstract: Disclosed embodiments relate to one or more techniques to control access by a requestor of a computing system to a shared memory resource. In one embodiment, a technique includes determining a number (N) of pending requests to be sent to the memory by the requestor, determining a number (M) of requests that the requestor is limited to sending based on an amount of buffering resources available, and comparing M to N. When N is both greater than zero and less than or equal to M, the requestor sends the N pending requests to the memory. When N is both greater than zero and greater than M, M is compared to a hysteresis value (R) and, when M is less than R, the requestor sends R of the N pending requests to the memory.

公开(公告)号：US12061909B2

公开(公告)日：2024-08-13

申请号：US18312380

申请日：2023-05-04

Applicant: International Business Machines Corporation

Inventor： Salma Ayub ,  Sundeep Chadha ,  Robert Allen Cordes ,  David Allen Hrusecky ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3802 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3885 ,  G06F12/0875 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/608

Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

公开(公告)号：US12061908B2

公开(公告)日：2024-08-13

申请号：US17472852

申请日：2021-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F9/32 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F12/02 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/16 ,  G06F13/40 ,  G06F11/10

CPC classification number: G06F9/321 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F12/0207 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/1605 ,  G06F13/4068 ,  G06F9/3836 ,  G06F11/10 ,  G06F2212/452 ,  G06F2212/60

Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

公开(公告)号：US12045614B2

公开(公告)日：2024-07-23

申请号：US17467550

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875

CPC classification number: G06F9/30043 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1064 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875 ,  G06F9/30047 ,  G06F11/10 ,  G06F2212/452 ,  G06F2212/621

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.

公开(公告)号：US20240211411A1

公开(公告)日：2024-06-27

申请号：US18587416

申请日：2024-02-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mujibur Rahman ,  Timothy David Anderson ,  Soujanya Narnur

IPC: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.