公开(公告)号：US10884735B2

公开(公告)日：2021-01-05

申请号：US15905623

申请日：2018-02-26

Applicant: Intel Corporation

Inventor： Jayesh Iyer ,  Jamison Collins ,  Sebastian Winkel ,  Howard Chen

IPC: G06F9/30

Abstract: A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.

公开(公告)号：US20190042247A1

公开(公告)日：2019-02-07

申请号：US15905623

申请日：2018-02-26

Applicant: Intel Corporation

Inventor： Jayesh Iyer ,  Jamison Collins ,  Sebastian Winkel ,  Howard Chen

IPC: G06F9/30

Abstract: A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.

公开(公告)号：US08843728B2

公开(公告)日：2014-09-23

申请号：US13682111

申请日：2012-11-20

Applicant: Intel Corporation

Inventor： Perry Wang ,  Jamison Collins ,  Hong Wang

IPC: G06F13/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F9/30 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3881 ,  G06F15/17368 ,  G06F15/7832

Abstract: In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer, detecting the assertion signal in the accelerators and communicating a request for a lock, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于将断言信号从第一指令定序器传送到耦合到第一指令定序器的多个加速器，检测加速器中的断言信号并传送锁定请求的方法， 加速器，其通过将加速器的注册消息通信给第一指令定序器来实现锁定。 描述和要求保护其他实施例。