公开(公告)号：US10528473B2

公开(公告)日：2020-01-07

申请号：US15621401

申请日：2017-06-13

Applicant: Intel Corporation

Inventor： Christopher Wilkerson ,  Muhammad M. Khellah ,  Vivek De ,  Ming Zhang ,  Jaume Abella ,  Javier Carretero Casado ,  Pedro Chaparro Monferrer ,  Xavier Vera ,  Antonio Gonzalez

IPC: G06F12/00 ,  G06F12/0864 ,  G06F12/0804 ,  G06F1/3234

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.