公开(公告)号：US09489342B2

公开(公告)日：2016-11-08

申请号：US14127178

申请日：2013-06-21

Applicant: Intel Corporation

Inventor： Niraj Gupta ,  Karthik N

IPC: G06F17/10 ,  G06F17/15 ,  G06F17/16

CPC classification number: G06F17/10 ,  G06F17/15 ,  G06F17/16

Abstract: The system has first, second, third, and fourth subsystems. Each subsystem has first and second multipliers coupled, respectively, to first and second adders. Each multiplier has two inputs. The first adder is coupled to a first output, a first accumulator, and a bit shifter. The bit shifter is coupled to a third adder. The third adder is coupled to a multiplexer. The multiplexer is coupled to a second output and a second accumulator. The second adder is coupled to the third adder and the multiplexer. The first outputs of the first and second subsystems are coupled directly to a fourth adder, the second outputs of the first and second subsystems are coupled directly to a fifth adder, the first outputs of the third and fourth subsystems are coupled directly to a sixth adder, and the second outputs of the third and fourth subsystems are coupled directly to a seventh adder.

Abstract translation: 该系统具有第一，第二，第三和第四子系统。 每个子系统具有分别耦合到第一和第二加法器的第一和第二乘法器。 每个乘法器有两个输入。 第一加法器耦合到第一输出，第一累加器和位移位器。 位移器耦合到第三加法器。 第三加法器耦合到多路复用器。 复用器耦合到第二输出和第二累加器。 第二加法器耦合到第三加法器和多路复用器。 第一和第二子系统的第一输出直接耦合到第四加法器，第一和第二子系统的第二输出直接耦合到第五加法器，第三和第四子系统的第一输出直接耦合到第六加法器 并且第三和第四子系统的第二输出直接耦合到第七加法器。