公开(公告)号：US20250094277A1

公开(公告)日：2025-03-20

申请号：US18966942

申请日：2024-12-03

Applicant: Intel Corporation

Inventor： Kishore KASICHAINULA ,  Thierry BEAUMONT ,  Dhanumjai PASUMARTHY ,  Sudhakar KAMMA

IPC: G06F11/10

Abstract: Methods and apparatus for low latency fail-operational Time Sensitive Networking. An apparatus includes an error detection and path switching (EDPS) circuit comprising circuitry to read data from volatile memory, detect whether read data is errant, the errant data including one or more uncorrectable errors, and send a message to access correct data corresponding to the errant data stored in a non-volatile memory device, the message identifying the correct data to be returned to the EDPS circuit. The apparatus receives the correct data and enables the correct data to be read by circuitry coupled to the EPDS circuit. The EDPS circuit includes Error Correction Code (ECC) logic to detect uncorrectable errors, detect the data has no ECC errors, and detect and correct single-bit errors to obtain corrected data. Data with no ECC errors and corrected data is immediately made available for reading by the circuitry coupled to the EPDS circuit.

公开(公告)号：US20230096468A1

公开(公告)日：2023-03-30

申请号：US18073221

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Boon Leong ONG ,  Kishore KASICHAINULA

IPC: H04L47/283 ,  H04L47/2441 ,  H04L49/00

Abstract: The present disclosure is generally related to network topologies and engineering, time-aware networks, time-sensitive applications, edge computing frameworks, data processing, network communication, and communication system implementations, and in particular, to techniques for providing in-transit packet detection to reduce real-time packet jitter. The present disclosure includes in-transit packet detectors inside a Medium Access Control (MAC) entity that observes received frames stored in a buffer, and provides in-transit received frame flag through a next bit of a descriptor. This provides a hint of received packet batch processing about in-transit receiver frames that should be processed in a current batch cycle.