公开(公告)号：US20230273821A1

公开(公告)日：2023-08-31

申请号：US18136262

申请日：2023-04-18

Applicant: Intel Corporation

Inventor： Amruta MISRA ,  Francesc GUIM BERNAT ,  Kshitij A. DOSHI ,  Marcos E. CARRANZA ,  John J. BROWNE ,  Arun HODIGERE

IPC: G06F9/48 ,  G06F11/34

CPC classification number: G06F9/4893 ,  G06F11/3433

Abstract: A method is described. The method includes dispatching jobs across electronic hardware components. The electronic hardware components are to process the jobs. The electronic hardware components are coupled to respective cooling systems. The respective cooling systems are each capable of cooling according to different cooling mechanisms. The different cooling mechanisms have different performance and cost operating realms. The dispatching of the jobs includes assigning the jobs to specific ones of the electronic hardware components to keep the cooling systems operating in one or more of the realms having lower performance and cost than another one of the realms.

公开(公告)号：US20220360646A1

公开(公告)日：2022-11-10

申请号：US17873618

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Kshitij A. DOSHI ,  Ned SMITH ,  Satish C. JHA ,  Vesh Raj SHARMA BANJADE ,  S M Iftekharul ALAM

IPC: H04L67/60 ,  H04L49/20 ,  H04L67/10

Abstract: Switching architectures to manage mutex primitives used to control access to objects or data blocks that are being processed by two or more microservices in a data center are provided.

公开(公告)号：US20220004873A1

公开(公告)日：2022-01-06

申请号：US17479858

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Suraj PRABHAKARAN ,  Kshitij A. DOSHI ,  Da-Ming CHIANG

IPC: G06N3/08 ,  G06N5/04 ,  G06N3/063

Abstract: Examples include techniques to manage training or trained models for deep learning applications. Examples include routing commands to configure a training model to be implemented by a training module or configure a trained model to be implemented by an inference module. The commands routed via out-of-band (OOB) link while training data for the training models or input data for the trained models are routed via inband links.

公开(公告)号：US20190140913A1

公开(公告)日：2019-05-09

申请号：US16235462

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Suraj PRABHAKARAN ,  Kshitij A. DOSHI ,  Brinda GANESH ,  Timothy VERRALL

IPC: H04L12/24 ,  G06N5/04 ,  G06N3/04

Abstract: Examples include techniques for artificial intelligence (AI) capabilities at a network switch. These examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an AI service to be provided by users requesting the AI service.

公开(公告)号：US20190065209A1

公开(公告)日：2019-02-28

申请号：US15984739

申请日：2018-05-21

Applicant: Intel Corporation

Inventor： Asit K. MISHRA ,  Kshitij A. DOSHI ,  Elmoustapha OULD-AHMED-VALL ,  Deborah T. MARR

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an execution unit, operatively coupled to the first register and the second register, the execution unit comprising a logic circuit implementing a sort instruction for sorting the plurality of data items stored in the first register in an order of data item values, and storing, in the second register, a plurality of indices, wherein each index identifies a position associated with a data item stored in the first register prior to the sorting.

公开(公告)号：US20190042936A1

公开(公告)日：2019-02-07

申请号：US15859472

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Suraj PRABHAKARAN ,  Kshitij A. DOSHI ,  Da-Ming CHIANG

IPC: G06N3/08 ,  G06N5/04

Abstract: Examples include techniques to manage training or trained models for deep learning applications. Examples include routing commands to configure a training model to be implemented by a training module or configure a trained model to be implemented by an inference module. The commands routed via out-of-band (OOB) link while training data for the training models or input data for the trained models are routed via inband links.

公开(公告)号：US20230421374A1

公开(公告)日：2023-12-28

申请号：US17809297

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Rajesh POORNACHANDRAN ,  Kshitij A. DOSHI ,  Rita H. WOUHAYBI ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Marcos CARRANZA ,  Cesar MARTINEZ SPESSOT

IPC: H04L9/30 ,  H04L9/32

CPC classification number: H04L9/30 ,  H04L9/3247

Abstract: Examples relate to a computer system, a telemetry hub apparatus, a telemetry hub device, a telemetry hub method, a microservice apparatus, a microservice device, a microservice method and to corresponding computer programs. The telemetry apparatus is configured to obtain telemetry information from a plurality of microservices, and to provide access to the telemetry information for the plurality of microservices according to an access scheme.

公开(公告)号：US20230115259A1

公开(公告)日：2023-04-13

申请号：US17877647

申请日：2022-07-29

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Suraj PRABHAKARAN ,  Alexander BACHMUTSKY ,  Raghu KONDAPALLI ,  Kshitij A. DOSHI

IPC: G06F18/214 ,  H04L67/1097 ,  G06N3/082 ,  H04L67/125 ,  H04L67/12 ,  G06N3/08 ,  H04L67/10 ,  G06N3/063

Abstract: An apparatus for training artificial intelligence (AI) models is presented. In embodiments, the apparatus may include an input interface to receive in real time model training data from one or more sources to train one or more artificial neural networks (ANNs) associated with the one or more sources, each of the one or more sources associated with at least one of the ANNs; a load distributor coupled to the input interface to distribute in real time the model training data for the one or more ANNs to one or more AI appliances; and a resource manager coupled to the load distributor to dynamically assign one or more computing resources on ones of the AI appliances to each of the ANNs in view of amounts of the training data received in real time from the one or more sources for their associated ANNs.

公开(公告)号：US20200348936A1

公开(公告)日：2020-11-05

申请号：US16927352

申请日：2020-07-13

Applicant: Intel Corporation

Inventor： Harshad S. SANE ,  Anup MOHAN ,  Kshitij A. DOSHI ,  Mark A. SCHMISSEUR

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0808

Abstract: A computing system includes a memory controller having a plurality of bypass parameters set by a software program, a thresholds matrix to store threshold values selectable by the plurality of bypass parameters, and a bypass function to determine whether a first cache line is to be displaced with a second cache line in a first memory or the first cache line remains in the first memory and the second cache line is to be accessed by at least one of a processor core and the cache from a second memory.

公开(公告)号：US20200242258A1

公开(公告)日：2020-07-30

申请号：US16845885

申请日：2020-04-10

Applicant: Intel Corporation

Inventor： Ned SMITH ,  Kshitij A. DOSHI ,  Francesc GUIM BERNAT ,  Kapil SOOD ,  Tarun VISWANATHAN

IPC: G06F21/60 ,  G06F15/173 ,  H04L9/32

Abstract: Examples herein relate to an interface selectively providing access to a memory region for a work request from an entity by providing selective access to a physical address of the memory region and selective access to a cryptographic key for use by a memory controller to access the memory region. In some examples, providing selective access to a physical address conversion is based on one or more of: validation of a certificate received with the work request and an identifier of the entity being associated with a process with access to the memory region. Access to the memory region can be specified to be one or more of: create, read, update, delete, write, or notify. A memory region can be a page or sub-page sized region. Different access rights can be associated with different sub-portions of the memory region, wherein the access rights comprise one or more of: create, read, update, delete, write, or notify.