公开(公告)号：US20210103481A1

公开(公告)日：2021-04-08

申请号：US16969728

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Francesc Guim BERNAT ,  Karthik KUMAR ,  Susanne M. BALLE ,  Ignacio ASTILLEROS DIEZ ,  Timothy VERRALL ,  Ned M. SMITH

IPC: G06F9/50 ,  G06F9/48

Abstract: Technologies for providing efficient migration of services include a server device. The server device includes compute engine circuitry to execute a set of services on behalf of a terminal device and migration accelerator circuitry. The migration accelerator circuitry is to determine whether execution of the services is to be migrated from an edge station in which the present server device is located to a second edge station in which a second server device is located, determine a prioritization of the services executed by the server device, and send, in response to a determination that the services are to be migrated and as a function of the determined prioritization, data utilized by each service to the second server device of the second edge station to migrate the services. Other embodiments are also described and claimed.

公开(公告)号：US20190140913A1

公开(公告)日：2019-05-09

申请号：US16235462

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Suraj PRABHAKARAN ,  Kshitij A. DOSHI ,  Brinda GANESH ,  Timothy VERRALL

IPC: H04L12/24 ,  G06N5/04 ,  G06N3/04

Abstract: Examples include techniques for artificial intelligence (AI) capabilities at a network switch. These examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an AI service to be provided by users requesting the AI service.

公开(公告)号：US20210034130A1

公开(公告)日：2021-02-04

申请号：US16524868

申请日：2019-07-29

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Suraj PRABHAKARAN ,  Karthik KUMAR ,  Uzair QURESHI ,  Timothy VERRALL

IPC: G06F1/30 ,  G06F1/26 ,  G06F11/14

Abstract: Examples described herein relate to management of battery-use by one or more computing resources in the event of a power outage. Data used by one or more computing resources can be backed-up using battery power. Battery power is allocated to data back-up operations based at least on one or more of: criticality level of data, priority of an application that processes the data, or priority level of resource. The computing resource can back-up data to a persistent storage media. The computing resource can store a log of data that is backed-up or not backed-up. The log can be used by the computing resource to access the backed-up data for continuing to process the data and to determine what data is not available for processing.

公开(公告)号：US20200241999A1

公开(公告)日：2020-07-30

申请号：US16829935

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Steven BRISCOE ,  Karthik KUMAR ,  Alexander BACHMUTSKY ,  Timothy VERRALL

IPC: G06F11/34

Abstract: Examples described herein relate to an apparatus that includes a memory and at least one processor where the at least one processor is to receive configuration to gather performance data for a function from one or more platforms and during execution of the function, collect performance data for the function and store the performance data after termination of execution of the function. Some examples include an interface coupled to the at least one processor and the interface is to receive one or more of: an identifier of a function, resources to be tracked as part of function execution, list of devices to be tracked as part of function execution, type of monitoring of function execution, or meta-data to identify when the function is complete. Performance data can be accessed to determine performance of multiple executions of the short-lived function.

公开(公告)号：US20190243685A1

公开(公告)日：2019-08-08

申请号：US16384554

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Felipe PASTOR BENEYTO ,  Kshitij A. DOSHI ,  Timothy VERRALL ,  Suraj PRABHAKARAN

IPC: G06F9/48 ,  G06F1/3296 ,  G06F1/20 ,  G06F9/50

CPC classification number: G06F9/4893 ,  G06F1/206 ,  G06F1/3296 ,  G06F9/4856 ,  G06F9/5027 ,  G06F2209/501

Abstract: Some examples provide for uninterruptible power supply form (UPS) resources and non-UPS resources to be offered in a composite node for customers to use. For a workload run on the composite node, monitoring of non-UPS resource power availability, resource temperature, and/or cooling facilities can take place. In the event, a non-UPS resource experiences a power outage or reduction in available power, temperature that is at or above a threshold level, and/or cooling facility outage, monitoring of performance of a workload executing on the non-UPS resource can take place. If the performance is acceptable and the power available to the non-UPS resource exceeds a threshold level, the supplied power can be reduced. If the performance experiences excessive levels of errors or slows unacceptably, the workload can be migrated to another non-UPS or UPS compliant resource.

公开(公告)号：US20180285563A1

公开(公告)日：2018-10-04

申请号：US15476827

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： John BROWNE ,  Vadim SUKHOMLINOV ,  Timothy VERRALL ,  Eoin WALSH

IPC: G06F21/55 ,  G06F21/45 ,  G06F21/12 ,  G06F21/53 ,  G06F21/32 ,  G06F21/54 ,  G06F21/56

Abstract: Examples include techniques for a service assurance using fingerprints associated with execution of virtualized applications. Examples include receiving information for computing events gathered while a virtual machine executes one or more applications to process a workload for a virtual network function over a period of time. A service performance risk may be reported based on a sample fingerprint generated using the gathered computing events.

公开(公告)号：US20240080246A1

公开(公告)日：2024-03-07

申请号：US18375934

申请日：2023-10-02

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Suraj PRABHAKARAN ,  Kshitij A. DOSHI ,  Brinda GANESH ,  Timothy VERRALL

IPC: H04L41/16 ,  G06N3/04 ,  G06N5/04 ,  H04L41/0816 ,  H04L41/5009 ,  H04L41/5019 ,  H04L41/5051

CPC classification number: H04L41/16 ,  G06N3/04 ,  G06N5/04 ,  H04L41/0816 ,  H04L41/5012 ,  H04L41/5019 ,  H04L41/5051

Abstract: Examples include techniques for artificial intelligence (AI) capabilities at a network switch. These examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an AI service to be provided by users requesting the AI service.

公开(公告)号：US20230205718A1

公开(公告)日：2023-06-29

申请号：US17561901

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Deepak S ,  Kannan Babu R. RAMIA ,  Palaniappan RAMANATHAN ,  Timothy VERRALL

IPC: G06F13/40 ,  G06F13/16 ,  G06F11/34 ,  G06F9/48

CPC classification number: G06F13/4022 ,  G06F13/1668 ,  G06F13/4068 ,  G06F11/3409 ,  G06F9/4881 ,  G06F2213/0026

Abstract: Examples described herein relate to a configurable switch with dynamically configurable device connections to a processor socket, where the device connections are configured to meet service level agreement (SLA) parameters of a first service executing on the processor socket. For a second service that is to execute on the processor socket and the second service is higher priority than the first service, device connections of the switch to the processor socket are dynamically reconfigured to meet SLA parameters of the second service.

公开(公告)号：US20220027278A1

公开(公告)日：2022-01-27

申请号：US17495454

申请日：2021-10-06

Applicant: Intel Corporation

Inventor： Piotr WYSOCKI ,  Francesc GUIM BERNAT ,  John J. BROWNE ,  Pawel ZAK ,  Rafal SZTEJNA ,  Przemyslaw PERYCZ ,  Timothy VERRALL ,  Szymon KONEFAL

IPC: G06F12/0862 ,  G06F9/48

Abstract: Examples include techniques for core-specific metrics collection. Examples include fetching metrics of a core of a multi-core processor from one or more registers responsive to scheduling of an event. The fetched metrics are pushed to a shared memory space of a memory that is accessible to a user-space application and accessible to other cores of the multi-core processor. The user-space application to access the shared memory space to aggregate core-specific metrics associated with at least the core of the multi-core processor and then publish the aggregated core-specific metrics.

公开(公告)号：US20210288793A1

公开(公告)日：2021-09-16

申请号：US17332733

申请日：2021-05-27

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Suraj PRABHAKARAN ,  Kshitij A. DOSHI ,  Timothy VERRALL

IPC: H04L9/08 ,  G06F3/06 ,  G06F9/50 ,  H04L29/06 ,  H04L29/08 ,  G06F16/25 ,  G06F16/2453 ,  H04L12/861 ,  G11C8/12 ,  G11C29/02 ,  H04L12/24 ,  G06F30/34 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G06F16/22 ,  G06F16/2455 ,  G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G06F15/173 ,  G06F13/40 ,  G06F13/42 ,  G06F9/448 ,  G06F9/28 ,  G06F15/16 ,  H04L12/703 ,  H04L12/743 ,  H04L12/801 ,  H04L12/803 ,  H04L12/935 ,  H04L12/931 ,  G06F9/4401 ,  G06F9/445 ,  G06F12/06 ,  G06F16/23 ,  G06F16/248 ,  G06F16/901 ,  G06F16/11

Abstract: Technologies for providing streamlined provisioning of accelerated functions in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to determine whether to accelerate a function of a workload executed by the compute sled, and send, to a memory sled and in response to a determination to accelerate the function, a data set on which the function is to operate. The circuitry is also to receive, from the memory sled, a service identifier indicative of a memory location independent handle for data associated with the function, send, to a compute device, a request to schedule acceleration of the function on the data set, receive a notification of completion of the acceleration of the function, and obtain, in response to receipt of the notification and using the service identifier, a resultant data set from the memory sled. The resultant data set was produced by an accelerator device during acceleration of the function on the data set. Other embodiments are also described and claimed.