公开(公告)号：US20230198815A1

公开(公告)日：2023-06-22

申请号：US17553918

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Lu LU ,  Sundar KRISHNAMURTHY ,  Kuilin Clark CHEN ,  Thushara HEWAVITHANA

IPC: H04L25/02 ,  H04B17/391

CPC classification number: H04L25/0256 ,  H04B17/391 ,  H04L25/0258 ,  H04L25/025 ,  H04L25/0252

Abstract: A distributed unit (DU) may include a transceiver configured to communicate with a plurality of radio units (RUs) that are configured to serve a plurality of user equipments (UEs). The DU may include a processor configured to determine RU precoding parameters for UEs served by a first RU set from the plurality of RUs based on estimated channel parameters for communication channels between the first RU set and at least one of interfering UEs served by other RUs from the plurality of RUs; to encode information indicating the determined precoding parameters for downlink transmissions to the first RU set and determine DU precoding parameters for downlink transmissions to the UEs served by the first RU set based on the determined RU precoding parameters; and/or precode communication signals based on the determined DU precoding parameters.

公开(公告)号：US20230205519A1

公开(公告)日：2023-06-29

申请号：US17560298

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Deepak DASALUKUNTE ,  Richard DORRANCE ,  Lu LU

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/3887

Abstract: A processor may include an interface configured to receive input data and instructions, and to provide processed data, a shared memory configured to store the received input data, an instruction memory configured to store the received instructions, a plurality of processing elements configured to perform a first set of arithmetic operations. The processor may further include a controller configured to control the plurality of processing elements and one or more accelerators based on the received instructions to obtain the processed data, by which the plurality of processing elements performs the first set of arithmetic operations and the one or more accelerators perform a second set of arithmetic operations based on the received input data stored in the shared memory.