公开(公告)号：US20200066326A1

公开(公告)日：2020-02-27

申请号：US15776058

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Rafael RIOS ,  Gilbert DEWEY ,  Van H. LE ,  Jack KAVALIEROS ,  Mesut METERELLIYOZ

IPC: G11C11/4097 ,  G11C11/405 ,  H01L27/108

Abstract: A high retention time memory element is described that has dual gate devices. In one example, the memory element has a write transistor with a metal gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.