公开(公告)号：US11171177B2

公开(公告)日：2021-11-09

申请号：US16243971

申请日：2019-01-09

Applicant: Intel Corporation

Inventor： Nathan A. Wilkerson ,  Mihir Bohra

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: A memory device includes a plurality of memory cells, a first nonconductive separator material separating the memory cells and having a word line end and bit line end, a metal via separated from the plurality of memory cells by a second nonconductive separator material, and metal bit line electrically connecting the metal via with the plurality of memory cells. The memory cells include a phase change material layer, a first electrode layer adjacent to the phase change material layer and having a phase change material layer side oriented toward the phase change material layer and a bit line side opposite the phase change material layer side, a metal silicon nitride layer on a surface of the bit line side of the first electrode layer. A bit line end surface of the first nonconductive separator material is at least partially free of contact with the metal silicon nitride layer.

公开(公告)号：US10658297B2

公开(公告)日：2020-05-19

申请号：US16024834

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Andrea Redaelli ,  D. Ross Economy ,  Mihir Bohra

IPC: H01L47/00 ,  H01L23/48 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/532 ,  G11C8/14 ,  H01L21/3205 ,  H01L23/522 ,  G11C7/18 ,  H01L27/24

Abstract: A nonvolatile memory device includes a metal silicon nitride layer on a three-dimensional (3D) crosspoint architecture, where the metal silicon nitride layer is in the memory array processing. The metal silicon nitride layer is patterned in accordance with the memory array structure, rather than being an underlying layer for a metal layer. The metal layer provides bitline or wordline select paths, and can connect to a via in parallel with the memory array stack. The metal silicon nitride layer is between the metal layer and the memory array, and is not present over the via.

公开(公告)号：US20190165046A1

公开(公告)日：2019-05-30

申请号：US16243971

申请日：2019-01-09

Applicant: Intel Corporation

Inventor： Nathan A. Wilkerson ,  Mihir Bohra

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: A memory device includes a plurality of memory cells, a first nonconductive separator material separating the memory cells and having a word line end and bit line end, a metal via separated from the plurality of memory cells by a second nonconductive separator material, and metal bit line electrically connecting the metal via with the plurality of memory cells. The memory cells include a phase change material layer, a first electrode layer adjacent to the phase change material layer and having a phase change material layer side oriented toward the phase change material layer and a bit line side opposite the phase change material layer side, a metal silicon nitride layer on a surface of the bit line side of the first electrode layer. A bit line end surface of the first nonconductive separator material is at least partially free of contact with the metal silicon nitride layer.