公开(公告)号：US11700209B2

公开(公告)日：2023-07-11

申请号：US16727543

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Robert Southworth ,  Karl S. Papadantonakis ,  Mika Nystroem ,  Arvind Srinivasan ,  David Arditti Ilitzky ,  Jonathan Dama

IPC: H04L47/625 ,  H04L49/901 ,  H04L67/568

CPC classification number: H04L47/6255 ,  H04L49/901 ,  H04L67/568

Abstract: Examples describe use of multiple meta-data delivery schemes to provide tags that describe packets to an egress port group. A tag, that is smaller than a packet, can be associated with a packet. The tag can be stored in a memory, as a group with other tags, and the tag can be delivered to a queue associated with an egress port. Packets received at an ingress port can be as non-interleaved to reduce underrun and providing cut-through to an egress port. A shared memory can be allocated to store packets received at a single ingress port or shared to store packets from multiple ingress ports.

公开(公告)号：US11671194B2

公开(公告)日：2023-06-06

申请号：US17527315

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Mark A. Bordogna ,  Janardhan H. Satyanarayana ,  Larry N. Wakeman ,  Robert G. Southworth ,  Mika Nystroem

IPC: H04J3/06 ,  H04L43/0852

CPC classification number: H04J3/0697 ,  H04L43/0852

Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.

公开(公告)号：US20220077946A1

公开(公告)日：2022-03-10

申请号：US17527315

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Mark A. Bordogna ,  Janardhan H. Satyanarayana ,  Larry N. Wakeman ,  Robert G. Southworth ,  Mika Nystroem

IPC: H04J3/06 ,  H04L12/26

Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.

公开(公告)号：US11212024B2

公开(公告)日：2021-12-28

申请号：US16476700

申请日：2017-04-07

Applicant: INTEL CORPORATION

Inventor： Mark A. Bordogna ,  Janardhan H. Satyanarayana ,  Larry N. Wakeman ,  Robert G. Southworth ,  Mika Nystroem

IPC: H04J3/06 ,  H04L12/26

Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.