公开(公告)号：US10509435B2

公开(公告)日：2019-12-17

申请号：US15279535

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Ramamurthy Krithivas ,  Mark A. Bordogna ,  James M. Sepko

IPC: G06F1/14 ,  G06F1/12 ,  G06F21/72 ,  G06F11/34

Abstract: Disclosed herein are systems and methods for initializing and synchronizing a protected real time clock via hardware connections. For example, in some embodiments, a protected real time clock on a trusted execution environment may initialize via a hardware connection to a master clock, which is synchronized to a trusted time source via a hardware connection. In some embodiments, a protected real time clock on a trusted execution environment may initialize to a master clock during a system hardware reset sequence. In some embodiments, before a system is running normally, a real time clock on an integrated Intellectual Property agent may initialize and synchronize to a protected real time clock via a hardware connection. In some embodiments, after a system is running normally, a real time clock on a discrete device may initialize and synchronize to a protected real time clock via a hardware connection.

公开(公告)号：US20190044839A1

公开(公告)日：2019-02-07

申请号：US15941854

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Yoni Landau ,  Janardhan H. Satyanarayana ,  Assaf Benhamou ,  Mark A. Bordogna

IPC: H04L12/26 ,  H04L29/06 ,  H04L1/00

Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.

公开(公告)号：US11212024B2

公开(公告)日：2021-12-28

申请号：US16476700

申请日：2017-04-07

Applicant: INTEL CORPORATION

Inventor： Mark A. Bordogna ,  Janardhan H. Satyanarayana ,  Larry N. Wakeman ,  Robert G. Southworth ,  Mika Nystroem

IPC: H04J3/06 ,  H04L12/26

Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.

公开(公告)号：US20220150149A1

公开(公告)日：2022-05-12

申请号：US17503817

申请日：2021-10-18

Applicant: Intel Corporation

Inventor： Yoni Landau ,  Janardhan H. Satyanarayana ,  Assaf BENHAMOU ,  Mark A. Bordogna

IPC: H04L43/106 ,  H04L69/22 ,  H04L1/00

Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.

公开(公告)号：US20180088625A1

公开(公告)日：2018-03-29

申请号：US15279535

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Ramamurthy Krithivas ,  Mark A. Bordogna ,  James M. Sepko

IPC: G06F1/14 ,  G06F1/12

Abstract: Disclosed herein are systems and methods for initializing and synchronizing a protected real time clock via hardware connections. For example, in some embodiments, a protected real time clock on a trusted execution environment may initialize via a hardware connection to a master clock, which is synchronized to a trusted time source via a hardware connection. In some embodiments, a protected real time clock on a trusted execution environment may initialize to a master clock during a system hardware reset sequence. In some embodiments, before a system is running normally, a real time clock on an integrated Intellectual Property agent may initialize and synchronize to a protected real time clock via a hardware connection. In some embodiments, after a system is running normally, a real time clock on a discrete device may initialize and synchronize to a protected real time clock via a hardware connection.

公开(公告)号：US11153191B2

公开(公告)日：2021-10-19

申请号：US15941854

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Yoni Landau ,  Janardhan H. Satyanarayana ,  Assaf Benhamou ,  Mark A. Bordogna

IPC: H04L12/26 ,  H04L29/06 ,  H04L1/00

Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.

公开(公告)号：US11671194B2

公开(公告)日：2023-06-06

申请号：US17527315

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Mark A. Bordogna ,  Janardhan H. Satyanarayana ,  Larry N. Wakeman ,  Robert G. Southworth ,  Mika Nystroem

IPC: H04J3/06 ,  H04L43/0852

CPC classification number: H04J3/0697 ,  H04L43/0852

Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.

公开(公告)号：US11546241B2

公开(公告)日：2023-01-03

申请号：US17503817

申请日：2021-10-18

Applicant: Intel Corporation

Inventor： Yoni Landau ,  Janardhan H. Satyanarayana ,  Assaf Benhamou ,  Mark A. Bordogna

IPC: H04L12/26 ,  H04L43/106 ,  H04L69/22 ,  H04L1/00

Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.

公开(公告)号：US20220077946A1

公开(公告)日：2022-03-10

申请号：US17527315

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Mark A. Bordogna ,  Janardhan H. Satyanarayana ,  Larry N. Wakeman ,  Robert G. Southworth ,  Mika Nystroem

IPC: H04J3/06 ,  H04L12/26

Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.