公开(公告)号：US11435909B2

公开(公告)日：2022-09-06

申请号：US16390551

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： Tonia G. Morris ,  Moshe Jacob Finkelstein ,  Ramesh Subashchandrabose ,  Lohit R. Yerva

IPC: G06F3/06 ,  G06N20/00

Abstract: Techniques and mechanisms for providing communications which facilitate link training. In an embodiment, a memory controller includes, or couples to, trainer circuitry which is configured to provide instructions to generate memory access commands. The instructions are accessed at the circuitry in response to an indication that link training is performed, where the accessing is independent of communication with a processor coupled to the memory controller. Based on the instructions, memory access commands are communicated via a link between the memory controller and a memory device. Link training is performed based on an evaluation of one or more characteristics of the link communications. In another embodiment, memory access commands are generated, based on the instructions, while a validity of data at the memory device is maintained.

公开(公告)号：US20200042209A1

公开(公告)日：2020-02-06

申请号：US16390551

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： Tonia G. Morris ,  Moshe Jacob Finkelstein ,  Ramesh Subashchandrabose ,  Lohit R. Yerva

IPC: G06F3/06 ,  G06N20/00

Abstract: Techniques and mechanisms for providing communications which facilitate link training. In an embodiment, a memory controller includes, or couples to, trainer circuitry which is configured to provide instructions to generate memory access commands. The instructions are accessed at the circuitry in response to an indication that link training is performed, where the accessing is independent of communication with a processor coupled to the memory controller. Based on the instructions, memory access commands are communicated via a link between the memory controller and a memory device. Link training is performed based on an evaluation of one or more characteristics of the link communications. In another embodiment, memory access commands are generated, based on the instructions, while a validity of data at the memory device is maintained.