公开(公告)号：US20200042209A1

公开(公告)日：2020-02-06

申请号：US16390551

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： Tonia G. Morris ,  Moshe Jacob Finkelstein ,  Ramesh Subashchandrabose ,  Lohit R. Yerva

IPC: G06F3/06 ,  G06N20/00

Abstract: Techniques and mechanisms for providing communications which facilitate link training. In an embodiment, a memory controller includes, or couples to, trainer circuitry which is configured to provide instructions to generate memory access commands. The instructions are accessed at the circuitry in response to an indication that link training is performed, where the accessing is independent of communication with a processor coupled to the memory controller. Based on the instructions, memory access commands are communicated via a link between the memory controller and a memory device. Link training is performed based on an evaluation of one or more characteristics of the link communications. In another embodiment, memory access commands are generated, based on the instructions, while a validity of data at the memory device is maintained.

公开(公告)号：US08745464B2

公开(公告)日：2014-06-03

申请号：US13968266

申请日：2013-08-15

Applicant: Intel Corporation

Inventor： Ramesh Subashchandrabose ,  Tessil Thomas ,  Sambaran Mitra ,  Debaleena Das ,  Kai Cheng

IPC: H03M13/00 ,  G11C29/00 ,  G06F12/06 ,  H03M13/03 ,  G06F11/10 ,  H03M13/09 ,  H03M13/15 ,  H03M13/19 ,  H04L1/00 ,  G06F12/02 ,  G11C8/12

CPC classification number: H03M13/03 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1064 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G06F12/02 ,  G11C8/12 ,  G11C29/00 ,  H03M13/09 ,  H03M13/15 ,  H03M13/19 ,  H04L1/0061

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract translation: 本公开的实施例描述了用于在存储器系统中提供排名特定循环冗余校验的方法，装置和系统配置。

公开(公告)号：US11435909B2

公开(公告)日：2022-09-06

申请号：US16390551

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： Tonia G. Morris ,  Moshe Jacob Finkelstein ,  Ramesh Subashchandrabose ,  Lohit R. Yerva

IPC: G06F3/06 ,  G06N20/00

Abstract: Techniques and mechanisms for providing communications which facilitate link training. In an embodiment, a memory controller includes, or couples to, trainer circuitry which is configured to provide instructions to generate memory access commands. The instructions are accessed at the circuitry in response to an indication that link training is performed, where the accessing is independent of communication with a processor coupled to the memory controller. Based on the instructions, memory access commands are communicated via a link between the memory controller and a memory device. Link training is performed based on an evaluation of one or more characteristics of the link communications. In another embodiment, memory access commands are generated, based on the instructions, while a validity of data at the memory device is maintained.