公开(公告)号：US20200075770A1

公开(公告)日：2020-03-05

申请号：US16122277

申请日：2018-09-05

Applicant: Intel Corporation

Inventor： Mauro J. KOBRINSKY ,  Stephanie BOJARSKI ,  Myra MCDONNELL ,  Tahir GHANI

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238

Abstract: Integrated circuit structures having differentiated neighboring partitioned source or drain contact structures are described. An integrated circuit structure includes a first gate stack over a first fin, and a second gate stack over a second fin. First and second epitaxial source or drain structures are at first and second ends of the first fin. Third and fourth epitaxial source or drain structures are at first and second ends of the second fin. A first conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures, and has a first portion partitioned from a second portion. A second conductive contact structure is coupled to one of the third or the fourth epitaxial source or drain structures, and has a first portion partitioned from a second portion. The second conductive contact structure is neighboring the first conductive contact structure and has a composition different than a composition of the first conductive contact structure.

公开(公告)号：US20200303191A1

公开(公告)日：2020-09-24

申请号：US16356402

申请日：2019-03-18

Applicant: Intel Corporation

Inventor： Anant JAHAGIRDAR ,  Chytra PAWASHE ,  Aaron LILAK ,  Myra MCDONNELL ,  Brennen MUELLER ,  Mauro KOBRINSKY

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/56

Abstract: Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.