公开(公告)号：US20240429161A1

公开(公告)日：2024-12-26

申请号：US18213963

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Tai-Hsuan Wu ,  Nikolay Ryzhenko Vladimirovich ,  Anand Krishnamoorthy ,  Mikhail Sergeevich Talalay ,  Xinning Wang ,  Quan Shi ,  Ozdemir Akin

IPC: H01L23/528 ,  H01L23/522

Abstract: Techniques are described for designing and forming cells having transistor devices. In an example, an integrated circuit structure includes a plurality of cells where adjacent cells have a decreased distance between them along their height and a staggered via arrangement. Accordingly, a first cell may be adjacent to a second cell along a shared cell boundary. A first via is provided between a first gate structure of the first cell adjacent to the cell boundary and a first metal layer above the first gate structure, and a second via is provided between a second gate structure of the second cell adjacent to the cell boundary and a second metal layer above the second gate structure. No part of the first via is aligned with any part of the second via along the first direction.

公开(公告)号：US20230397410A1

公开(公告)日：2023-12-07

申请号：US17834679

申请日：2022-06-07

Applicant: Intel Corporation

Inventor： Pulkit Jain ,  Juan Alzate Vinasco ,  Liqiong Wei ,  Ozdemir Akin ,  Fatih Hamzaoglu

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4091

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  G11C11/4085 ,  G11C11/4091

Abstract: Techniques and mechanisms for accessing memory arrays which are formed in a back end of line (BEOL) of an integrated circuit (IC) die. In an embodiment, a differential sense amplifier of the IC die is coupled to a first array and a second array via a first bit line and a second bit line, respectively. The first bit line and the second bit line extend from a first level of BEOL memory arrays, toward a front end of line (FEOL) of the IC die, on opposite respective sides of first array, wherein the differential sense amplifier is in a footprint region for the first memory array. In another embodiment, a word line driver circuit comprises a two stage charger-discharger circuit which mitigates hot carrier injection.