公开(公告)号：US11610894B2

公开(公告)日：2023-03-21

申请号：US16457657

申请日：2019-06-28

申请人： Intel Corporation

发明人： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Yu-Wen Huang ,  Shu Zhou

IPC分类号： H01L27/108

摘要： Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US11450669B2

公开(公告)日：2022-09-20

申请号：US16043548

申请日：2018-07-24

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Umut Arslan ,  Travis W. Lajoie ,  Chieh-jen Ku

IPC分类号： H01L27/108 ,  G11C7/06 ,  G11C11/407 ,  H01L23/00 ,  H01L25/065 ,  H01L27/06 ,  H01L29/417 ,  H01L29/786 ,  H01L27/11

摘要： Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20200005866A1

公开(公告)日：2020-01-02

申请号：US16023728

申请日：2018-06-29

申请人： Intel Corporation

发明人： Pulkit Jain ,  Umut Arslan ,  Fatih Hamzaoglu

IPC分类号： G11C13/00 ,  G11C7/06 ,  G11C8/10

摘要： Some embodiments include apparatuses having a resistive memory device and methods to apply a combination of voltage stepping current stepping and pulse width stepping during an operation of changing a resistance of a memory cell of the resistive memory device. The apparatuses also include a write termination circuit to limit drive current provided to a memory cell of the resistive memory device during a particular time of an operation performed on the memory cell. The apparatuses further include a programmable variable resistor and resistor control circuit that operate during sensing operation of the memory device.

公开(公告)号：US09865322B2

公开(公告)日：2018-01-09

申请号：US15280935

申请日：2016-09-29

申请人： Intel Corporation

发明人： Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

IPC分类号： G11C11/16 ,  G06F3/06

CPC分类号： G11C11/1675 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

摘要： Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

公开(公告)号：US10438640B2

公开(公告)日：2019-10-08

申请号：US16052552

申请日：2018-08-01

申请人： Intel Corporation

发明人： Liqiong Wei ,  Fatih Hamzaoglu ,  Yih Wang ,  Nathaniel J. August ,  Blake C. Lin ,  Cyrille Dray

IPC分类号： G11C11/16 ,  G11C29/02 ,  G11C13/00

摘要： Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US10068628B2

公开(公告)日：2018-09-04

申请号：US14129277

申请日：2013-06-28

申请人： Intel Corporation

发明人： Liqiong Wei ,  Fatih Hamzaoglu ,  Yih Wang ,  Nathaniel J. August ,  Blake C. Lin ,  Cyrille Dray

IPC分类号： G11C11/16 ,  G11C29/02 ,  G11C13/00

摘要： Apparatuses for improving resistive memory energy efficiency are provided. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US09666268B2

公开(公告)日：2017-05-30

申请号：US14703723

申请日：2015-05-04

申请人： Intel Corporation

发明人： Yih Wang ,  Muhammad M. Khellah ,  Fatih Hamzaoglu

IPC分类号： G11C7/00 ,  G11C11/419 ,  G11C5/14 ,  G11C11/4074

CPC分类号： G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

摘要： Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

公开(公告)号：US20220415896A1

公开(公告)日：2022-12-29

申请号：US17358930

申请日：2021-06-25

申请人： Intel Corporation

发明人： Juan G. Alzate-Vinasco ,  Travis W. LaJoie ,  Wilfred Gomes ,  Fatih Hamzaoglu ,  Pulkit Jain ,  James Waldemer ,  Mark Armstrong ,  Bernhard Sell ,  Pei-Hua Wang ,  Chieh-Jen Ku

IPC分类号： H01L27/108 ,  H01L29/786 ,  H01L29/66

摘要： A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

公开(公告)号：US11462541B2

公开(公告)日：2022-10-04

申请号：US16222934

申请日：2018-12-17

申请人： Intel Corporation

发明人： Juan G. Alzate Vinasco ,  Abhishek A. Sharma ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-Hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Chieh-Jen Ku ,  Travis W. Lajoie ,  Umut Arslan

IPC分类号： H01L21/00 ,  H01L27/108 ,  H01L29/786 ,  H01L49/02 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417

摘要： Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US11094358B2

公开(公告)日：2021-08-17

申请号：US16319239

申请日：2016-09-30

申请人： Intel Corporation

发明人： Ilya Karpov ,  Yih Wang ,  Fatih Hamzaoglu ,  James Clarke

IPC分类号： H01L21/02 ,  G11C11/00 ,  G11C11/22 ,  G11C11/407 ,  H01L27/108 ,  H01L27/11514 ,  H01L27/11507 ,  G11C11/401

摘要： An apparatus is described. The apparatus includes a semiconductor chip that includes logic circuitry, embedded dynamic random access memory (DRAM) cells and embedded ferroelectric random access memory (FeRAM) cells.