公开(公告)号：US20220295160A1

公开(公告)日：2022-09-15

申请号：US17830223

申请日：2022-06-01

Applicant: Intel Corporation

Inventor： Junyuan WANG ,  Timothy WAITE ,  Ziye YANG ,  Zijuan FAN ,  Yao HUO ,  Weigang LI ,  Yuze XIAO ,  Greg THOMAS ,  Qianjun XIE

IPC: H04Q9/00 ,  G06F21/72

Abstract: Examples described herein relate to circuitry to provide telemetry data of first circuitry based on a power state of the first circuitry and provide telemetry data of second circuitry based on a power state of the second circuitry.

公开(公告)号：US20240020241A1

公开(公告)日：2024-01-18

申请号：US18254322

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Kaijie GUO ,  Weigang LI ,  Junyuan WANG ,  Bo CUI ,  Mithilesh K. DAS ,  Amit K. WARDHAN ,  Zijuan FAN ,  Maojun JI ,  Qianjun XIE ,  Tingqiang CHU

IPC: G06F12/1081

CPC classification number: G06F12/1081 ,  G06F2212/657

Abstract: Apparatus and method for performing address pre-translation to enhance direct memory access by hardware subsystems is described herein. An apparatus embodiment includes a processor to execute an enqueue instruction to submit, to a hardware subsystem, a job descriptor describing a job to be performed. The job descriptor includes virtual addresses of memory locations in which data required to perform the job are stored. An input-output memory management unit (IOMMU) is to obtain the address translations for the virtual addresses responsive to a pre-translation request from the processor. The address translations is obtained by the IOMMU prior to receiving a memory access request from the hardware subsystem. The IOMMU is to retrieve the data from the memory location using the address translations and to provide the retrieved data to the hardware subsystem to fulfill the request.