公开(公告)号：US10091216B2

公开(公告)日：2018-10-02

申请号：US15081992

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Gal Chanoch ,  Eran Birk ,  Baiju Patel ,  Steven Grobman ,  Tobias Kohlenberg ,  Rajeev Gopalakrishna

IPC: H04L29/06 ,  G06F21/54

Abstract: Technologies are provided in embodiments for receiving policy information associated with at least one security exception, the security exception relating to execution of at least one program, determining an operation associated with the security exception based, at least in part, on the policy information, and causing the operation to be performed, based at least in part, on a determination that the at least one security exception occurred.

公开(公告)号：US20160323297A1

公开(公告)日：2016-11-03

申请号：US15081992

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Gal Chanoch ,  Eran Birk ,  Baiju Patel ,  Steven Grobman ,  Tobias Kohlenberg ,  Rajeev Gopalakrishna

IPC: H04L29/06

CPC classification number: H04L63/1408 ,  G06F21/54 ,  H04L63/10

Abstract: Technologies are provided in embodiments for receiving policy information associated with at least one security exception, the security exception relating to execution of at least one program, determining an operation associated with the security exception based, at least in part, on the policy information, and causing the operation to be performed, based at least in part, on a determination that the at least one security exception occurred.

Abstract translation: 在用于接收与至少一个安全异常相关联的策略信息，与至少一个程序的执行有关的安全异常，至少部分地基于策略信息确定与所述安全异常相关联的操作的实施例中提供技术，以及 至少部分地基于确定发生了至少一个安全异常来执行操作。

公开(公告)号：US10162640B2

公开(公告)日：2018-12-25

申请号：US15238703

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Martin G. Dixon ,  Baiju V. Patel ,  Rajeev Gopalakrishna

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

Abstract: A processor is described having a functional unit within an instruction execution pipeline. The functional unit having circuitry to determine whether substantive data from a larger source data size will fit within a smaller data size that the substantive data is to flow to.

公开(公告)号：US09417880B2

公开(公告)日：2016-08-16

申请号：US13843558

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Martin Dixon ,  Baiju Patel ,  Rajeev Gopalakrishna

IPC: G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30076 ,  G06F9/3802 ,  G06F9/3838 ,  G06F9/3861

Abstract: A processor is described having a functional unit within an instruction execution pipeline. The functional unit having circuitry to determine whether substantive data from a larger source data size will fit within a smaller data size that the substantive data is to flow to.

Abstract translation: 描述了处理器在指令执行流水线内具有功能单元。 功能单元具有用于确定来自较大源数据大小的实质数据是否适合实质数据要流向的较小数据大小的电路。