公开(公告)号：US20250103509A1

公开(公告)日：2025-03-27

申请号：US18475104

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Ramya Prabhu ,  Joydeep Rakshit ,  Anant Vithal Nori ,  Stanislav Shwartsman

IPC: G06F12/1027 ,  G06F12/02 ,  G06F12/121

Abstract: Techniques for victim buffering through translation lookaside buffer (TLB) partitioning are described. In certain examples, a system includes a memory; an execution circuitry to generate a memory access request for a virtual memory address of the memory; a first level translation lookaside buffer to store virtual address to physical address mappings; a victim translation lookaside buffer to store a virtual address to physical address mapping evicted from the first level translation lookaside buffer; a second level translation lookaside buffer; and a cache coherency circuitry to search the first level translation lookaside buffer and the victim translation lookaside buffer for a corresponding physical address mapped to the virtual memory address for the memory access request, and for a miss in the first level translation lookaside buffer and the victim translation lookaside buffer, search the second level translation lookaside buffer for the corresponding physical address mapped to the virtual memory address for the memory access request, and for a hit in the victim translation lookaside buffer, provide the corresponding physical address mapped to the virtual memory address for the memory access request.