公开(公告)号：US11972126B2

公开(公告)日：2024-04-30

申请号：US17472272

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： David M. Durham ,  Michael D. LeMay ,  Sergej Deutsch ,  Joydeep Rakshit ,  Anant Vithal Nori ,  Jayesh Gaur ,  Sreenivas Subramoney

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1027

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0238 ,  G06F12/1027

Abstract: Technologies disclosed herein provide one example of a system that includes processor circuitry to be communicatively coupled to a memory circuitry. The processor circuitry is to receive a memory access request corresponding to an application for access to an address range in a memory allocation of the memory circuitry and to locate a metadata region within the memory allocation. The processor circuitry is also to, in response to a determination that the address range includes at least a portion of the metadata region, obtain first metadata stored in the metadata region, use the first metadata to determine an alternate memory address in a relocation region, and read, at the alternate memory address, displaced data from the portion of the metadata region included in the address range of the memory allocation. The address range includes one or more bytes of an expected allocation region of the memory allocation.

公开(公告)号：US12112171B2

公开(公告)日：2024-10-08

申请号：US17134367

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Anant Nori ,  Shankar Balachandran ,  Sreenivas Subramoney ,  Joydeep Rakshit ,  Vedvyas Shanbhogue ,  Avishaii Abuhatzera ,  Belliappa Kuttanna

IPC: G06F8/41 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/30145 ,  G06F9/30065 ,  G06F9/3836 ,  G06F9/4881

Abstract: Techniques for processing loops are described. An exemplary apparatus at least includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode, the opcode to indicate execution circuitry is to perform an operation to configure execution of one or more loops, wherein the one or more loops are to include a plurality of configuration instructions and instructions that are to use metadata generated by ones of the plurality of configuration instructions; and execution circuitry to perform the operation as indicated by the opcode.

公开(公告)号：US20250103509A1

公开(公告)日：2025-03-27

申请号：US18475104

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Ramya Prabhu ,  Joydeep Rakshit ,  Anant Vithal Nori ,  Stanislav Shwartsman

IPC: G06F12/1027 ,  G06F12/02 ,  G06F12/121

Abstract: Techniques for victim buffering through translation lookaside buffer (TLB) partitioning are described. In certain examples, a system includes a memory; an execution circuitry to generate a memory access request for a virtual memory address of the memory; a first level translation lookaside buffer to store virtual address to physical address mappings; a victim translation lookaside buffer to store a virtual address to physical address mapping evicted from the first level translation lookaside buffer; a second level translation lookaside buffer; and a cache coherency circuitry to search the first level translation lookaside buffer and the victim translation lookaside buffer for a corresponding physical address mapped to the virtual memory address for the memory access request, and for a miss in the first level translation lookaside buffer and the victim translation lookaside buffer, search the second level translation lookaside buffer for the corresponding physical address mapped to the virtual memory address for the memory access request, and for a hit in the victim translation lookaside buffer, provide the corresponding physical address mapped to the virtual memory address for the memory access request.

公开(公告)号：US20210405896A1

公开(公告)日：2021-12-30

申请号：US17472272

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： David M. Durham ,  Michael D. LeMay ,  Sergej Deutsch ,  Joydeep Rakshit ,  Anant Vithal Nori ,  Jayesh Gaur ,  Sreenivas Subramoney

IPC: G06F3/06 ,  G06F12/1027 ,  G06F12/02

Abstract: Technologies disclosed herein provide one example of a system that includes processor circuitry to be communicatively coupled to a memory circuitry. The processor circuitry is to receive a memory access request corresponding to an application for access to an address range in a memory allocation of the memory circuitry and to locate a metadata region within the memory allocation. The processor circuitry is also to, in response to a determination that the address range includes at least a portion of the metadata region, obtain first metadata stored in the metadata region, use the first metadata to determine an alternate memory address in a relocation region, and read, at the alternate memory address, displaced data from the portion of the metadata region included in the address range of the memory allocation. The address range includes one or more bytes of an expected allocation region of the memory allocation.