公开(公告)号：US11126430B2

公开(公告)日：2021-09-21

申请号：US16729253

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Parakalan Venkataraghavan ,  Thomas W. Smith ,  Silpa Naidu Chirumavilla ,  Ravi Shekhar

IPC: G06F9/30 ,  G06F9/38

Abstract: A vector processor includes a grouping memory functional unit coupled to grouping memory having multiple bins. The vector processor also includes a bitformatting functional unit that performs bit-level data arrangements using any suitable technique or network, such as a Benes network. The vector processor receives and reads an input vector of data that includes portions (e.g., bits) of multiple data streams, and writes each portion corresponding to a respective data stream to a respective bin in parallel using the bitformatting functional unit to align the data. The vector processor also or alternatively receives and reads multiple outgoing data streams, writes portions of the data streams in respective bins of the grouping memory, and intersperses the portions in an outgoing vector of data in parallel, using the bitformatting functional unit to align the data.