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    Vector processor for heterogeneous data streams
    1.
    发明授权
    Vector processor for heterogeneous data streams 有权

    公开(公告)号：US11126430B2

    公开(公告)日：2021-09-21

    申请号：US16729253

    申请日：2019-12-27

    Applicant: Intel Corporation

    Inventor： Parakalan Venkataraghavan ,  Thomas W. Smith ,  Silpa Naidu Chirumavilla ,  Ravi Shekhar

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A vector processor includes a grouping memory functional unit coupled to grouping memory having multiple bins. The vector processor also includes a bitformatting functional unit that performs bit-level data arrangements using any suitable technique or network, such as a Benes network. The vector processor receives and reads an input vector of data that includes portions (e.g., bits) of multiple data streams, and writes each portion corresponding to a respective data stream to a respective bin in parallel using the bitformatting functional unit to align the data. The vector processor also or alternatively receives and reads multiple outgoing data streams, writes portions of the data streams in respective bins of the grouping memory, and intersperses the portions in an outgoing vector of data in parallel, using the bitformatting functional unit to align the data.

    Apparatuses, methods, and systems for a user defined formatting instruction to configure multicast Benes network circuitry
    2.
    发明授权
    Apparatuses, methods, and systems for a user defined formatting instruction to configure multicast Benes network circuitry 有权

    公开(公告)号：US11334356B2

    公开(公告)日：2022-05-17

    申请号：US16457994

    申请日：2019-06-29

    Applicant: Intel Corporation

    Inventor： Jian-Guo Chen ,  David T. Dougherty ,  Steven Pinault ,  Parakalan Venkataraghavan ,  Joseph Williams ,  Meng-Lin Yu ,  Kamran Azadet

    IPC: G06F9/30 ,  H04L49/25 ,  H04L49/201 ,  G06F9/54

    Abstract: Systems, methods, and apparatuses relating to a user defined formatting instruction to configure multicast Benes network circuitry are described. In one embodiment, a processor includes a decoder to decode a single instruction into a decoded single instruction, the single instruction having fields that identify packed input data, packed control data, and a packed data destination; and an execution unit to execute the decoded single instruction to: send the packed control data to respective control inputs of a circuit that comprises an inverse butterfly circuit coupled in series to a butterfly circuit, wherein the inverse butterfly circuit comprises a first plurality of stages of multicast switches and the butterfly circuit comprises a second plurality of stages of multicast switches, read, once from storage separate from the circuit, each element of the packed input data as respective inputs of the circuit, route the packed input data through the circuit according to the packed control data, and store resultant packed data from the circuit into the packed data destination.

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