公开(公告)号：US20210026769A1

公开(公告)日：2021-01-28

申请号：US17042037

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Malini K. BHANDARU ,  Iosif GASPARAKIS ,  Sunku RANGANATH ,  Liyong QIAO ,  Rui ZANG ,  Dakshina ILANGOVAN ,  Shaohe FENG ,  Edwin VERPLANKE ,  Priya AUTEE ,  Lin A. YANG

IPC: G06F12/0806 ,  G06F9/54 ,  G06F9/50

Abstract: Examples include techniques to support a holistic view of cache class of service (CLOS). Examples include allocating processor cache resources to a plurality of CLOS. The allocation of processor cache resources to include allocation of cache ways for an n-way set of associative cache. Examples include monitoring usage of the plurality of CLOS to determine processor cache resource usage and to report the processor cache resource usage.

公开(公告)号：US20230088347A1

公开(公告)日：2023-03-23

申请号：US18071436

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Hong ZHANG ,  Yingchun GUO ,  Rui ZANG ,  Xinran WANG

IPC: G06F9/455

Abstract: Examples described herein relate to a system that prior to execution of a virtualized execution environment on a compute node, store at least one image block into at least one tier of storage of a hierarchical storage system based on priority of the at least one image block. In some examples, the at least one image block comprises at least one portion of an image of the virtualized execution environment.

公开(公告)号：US20230118994A1

公开(公告)日：2023-04-20

申请号：US17991807

申请日：2022-11-21

Applicant: Intel Corporation

Inventor： Hong ZHANG ,  Rui ZANG ,  Xinran WANG ,  Yingchun GUO

IPC: G06F3/06 ,  G06F16/185

Abstract: Examples described herein relate to selecting a compute node to execute the function based on latency of retrievals of function data blocks, wherein the function data blocks comprise at least a portion of an image of the function and the function data blocks are stored among two or more tiers of storage. In some examples, a latency of retrievals of function data blocks is based on storage of the function data blocks in devices of one or more storage tiers and retrieval latency to a memory utilized to launch the function.