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    CACHE LINE DEMOTE INFRASTRUCTURE FOR MULTI-PROCESSOR PIPELINES
    1.
    发明申请
    CACHE LINE DEMOTE INFRASTRUCTURE FOR MULTI-PROCESSOR PIPELINES 有权

    公开(公告)号：US20210073129A1

    公开(公告)日：2021-03-11

    申请号：US17086243

    申请日：2020-10-30

    Applicant: Intel Corporation

    Inventor： Rahul R. SHAH ,  Omkar MASLEKAR ,  Priya AUTEE ,  Edwin VERPLANKE ,  Andrew J. HERDRICH ,  Jeffrey D. CHAMBERLAIN

    IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/1009 ,  G06F9/30

    Abstract: Examples described herein relate to a manner of demoting multiple cache lines to shared memory. In some examples, a shared cache is accessible by at least two processor cores and a region of the cache is larger than a cache line and is designated for demotion from the cache to the shared cache. In some examples, the cache line corresponds to a memory address in a region of memory. In some examples, an indication that the region of memory is associated with a cache line demote operation is provided in an indicator in a page table entry (PTE). In some examples, the indication that the region of memory is associated with a cache line demote operation is based on a command in an application executed by a processor. In some examples, the cache is an level 1 (L1) or level 2 (L2) cache.

    CONTROLLER FOR LOCKING OF SELECTED CACHE REGIONS
    2.
    发明申请
    CONTROLLER FOR LOCKING OF SELECTED CACHE REGIONS 审中-公开

    公开(公告)号：US20190340123A1

    公开(公告)日：2019-11-07

    申请号：US16514226

    申请日：2019-07-17

    Applicant: Intel Corporation

    Inventor： Andrew J. HERDRICH ,  Priya AUTEE ,  Abhishek KHADE ,  Patrick LU ,  Edwin VERPLANKE ,  Vivekananthan SANJEEPAN

    IPC: G06F12/0802

    Abstract: Examples provide an application program interface or manner of negotiating locking or pinning or unlocking or unpinning of a cache region by which an application, software, or hardware. A cache region can be part of a level-1, level-2, lower or last level cache (LLC), or translation lookaside buffer (TLB) are locked (e.g., pinned) or unlocked (e.g., unpinned). A cache lock controller can respond to a request to lock or unlock a region of cache or TLB by indicating that the request is successful or not successful. If a request is not successful, the controller can provide feedback indicating one or more aspects of the request that are not permitted. The application, software, or hardware can submit another request, a modified request, based on the feedback to attempt to lock a portion of the cache or TLB.

    CONTROLLER FOR LOCKING OF SELECTED CACHE REGIONS
    5.
    发明申请
    CONTROLLER FOR LOCKING OF SELECTED CACHE REGIONS 有权

    公开(公告)号：US20210042228A1

    公开(公告)日：2021-02-11

    申请号：US17069819

    申请日：2020-10-13

    Applicant: Intel Corporation

    Inventor： Andrew J. HERDRICH ,  Priya AUTEE ,  Abhishek KHADE ,  Patrick LU ,  Edwin VERPLANKE ,  Vedvyas SHANBHOGUE

    IPC: G06F12/0811 ,  G06F12/0891 ,  G06F12/06 ,  G06F12/1027 ,  G06F12/14 ,  G06F9/30 ,  G06F9/455

    Abstract: Examples provide a system that includes at least one processor; a cache; a memory; an interface to copy data from a received packet to the memory or the at least one cache; and controller to manage use of at least one region of the cache. In some examples, the controller is to: indicate availability of a cache region reservation feature; receive a request to reserve a region of the cache from a requester; and based on the requested region being permitted to be reserved by the requester, solely allow the requester to write data to at least a portion of the reserved region. In some examples, the controller is to write to a register to indicate availability of a cache region reservation feature. In some examples, the request to reserve a region of the cache from a requester comprises a specification of a number of sets, a number of ways, and a class of service.

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