公开(公告)号：US20230091834A1

公开(公告)日：2023-03-23

申请号：US17482380

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Bainye Francoise ANGOUA ,  Ala OMER ,  Sarah BLYTHE ,  Junxin WANG ,  Whitney BRYKS ,  Dilan SENEVIRATNE ,  Jieying KONG

IPC: G02B6/125 ,  G02B6/13

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed an optical waveguide formed in a glass layer. The optical waveguide may be formed by creating a first trench extending from a surface of the glass layer, and then creating a second trench extending from the bottom of the first trench, then subsequently filling the trenches with a core material which may then be topped with a cladding material. Other embodiments may be described and/or claimed.

公开(公告)号：US20230090863A1

公开(公告)日：2023-03-23

申请号：US17482384

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Dilan SENEVIRATNE ,  Whitney BRYKS ,  Ala OMER ,  Jieying KONG ,  Sarah BLYTHE ,  Bainye Francoise ANGOUA

IPC: G02B6/42 ,  G02B6/12

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to dense integration of PICs in a substrate using an optical fanout structure that includes waveguides formed within a substrate to optically couple with the PICs at an edge of the substrate. One or more PICs may then be electrically with dies such as processor dies or memory dies. The one or more PICs may be located within a cavity in the substrate. The substrate may be made of glass or silicon. Other embodiments may be described and/or claimed.

公开(公告)号：US20230098501A1

公开(公告)日：2023-03-30

申请号：US17485375

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Sarah BLYTHE ,  Jieying KONG ,  Peumie ABEYRATNE KURAGAMA ,  Hongxia FENG

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/532

Abstract: A system includes a metallic contact integrated onto a semiconductor integrated circuit substrate with a stress buffer dielectric between the contact and the bulk dielectric. The bulk dielectric typically covers an integrated circuit metal layer to provide electrical isolation of the circuitry. The semiconductor circuit can include a trace that connects the contact to a package pad to enable external access to the signal from off the semiconductor circuit. The stress buffer dielectric has higher elongation and lower filler loading relative to the bulk dielectric, which makes the stress buffer more pliable. The stress buffer is disposed between the contact and the bulk dielectric to improve stress response, reducing the possibility of delamination of the contact from the bulk dielectric.

公开(公告)号：US20230086881A1

公开(公告)日：2023-03-23

申请号：US17481247

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Whitney BRYKS ,  Jieying KONG ,  Bainye Francoise ANGOUA ,  Junxin WANG ,  Sarah BLYTHE ,  Ala OMER ,  Dilan SENEVIRATNE

IPC: G02B6/43 ,  G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a double-sided glass substrate, to which a PIC is hybrid bonded to a first side of the glass substrate. A die is coupled with the second side of the glass substrate opposite the first side, the PIC and the die are electrically coupled with electrically conductive through glass vias that extend from the first side of the glass substrate to the second side of the glass substrate. Other embodiments may be described and/or claimed.