公开(公告)号：US20230090863A1

公开(公告)日：2023-03-23

申请号：US17482384

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Dilan SENEVIRATNE ,  Whitney BRYKS ,  Ala OMER ,  Jieying KONG ,  Sarah BLYTHE ,  Bainye Francoise ANGOUA

IPC: G02B6/42 ,  G02B6/12

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to dense integration of PICs in a substrate using an optical fanout structure that includes waveguides formed within a substrate to optically couple with the PICs at an edge of the substrate. One or more PICs may then be electrically with dies such as processor dies or memory dies. The one or more PICs may be located within a cavity in the substrate. The substrate may be made of glass or silicon. Other embodiments may be described and/or claimed.

公开(公告)号：US20230090188A1

公开(公告)日：2023-03-23

申请号：US17481001

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Junxin WANG ,  Kemal AYGUN ,  Jieying KONG ,  Ala OMER ,  Whitney M. BRYKS

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538

Abstract: An apparatus is described. The apparatus includes a semiconductor chip package substrate having alternating metal and dielectric layers. First and second ones of the dielectric layers that are directly above and directly below a first of the metal layers that is patterned to have supply and/or reference voltage structures have respectively higher dielectric constant (Dk) and higher dissipation factor (Df) than third and fourth ones of the dielectric layers that are directly above and directly below a second of the metal layers that is patterned to have signal wires that are to transport signals having a pulse width of 1 ns or less.

公开(公告)号：US20230086881A1

公开(公告)日：2023-03-23

申请号：US17481247

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Whitney BRYKS ,  Jieying KONG ,  Bainye Francoise ANGOUA ,  Junxin WANG ,  Sarah BLYTHE ,  Ala OMER ,  Dilan SENEVIRATNE

IPC: G02B6/43 ,  G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a double-sided glass substrate, to which a PIC is hybrid bonded to a first side of the glass substrate. A die is coupled with the second side of the glass substrate opposite the first side, the PIC and the die are electrically coupled with electrically conductive through glass vias that extend from the first side of the glass substrate to the second side of the glass substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222089A1

公开(公告)日：2024-07-04

申请号：US18090400

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ala OMER ,  Peumie ABEYRATNE KURAGAMA ,  Jieying KONG ,  Wendy LIN ,  Ao WANG

IPC: H01J37/32 ,  H01L21/3105

CPC classification number: H01J37/32715 ,  H01L21/31058 ,  H01J2237/2007 ,  H01J2237/20235 ,  H01J2237/334 ,  H01J2237/3355 ,  H01J2237/336 ,  H01L21/02063

Abstract: This disclosure describes designs and methods for via cleaning, peeling protective film, and providing mild surface roughening and cleaning of a computer chip. A system may include a first electrode configured to generate plasma associated with cleaning vias by etching a residual material associated with smearing; an electrostatic stage configured to generate an electrostatic force associated with peeling the dielectric protective film from the semiconductor; and a stage on which the semiconductor is positioned while the electrostatic stage peels the dielectric protective film from the semiconductor, wherein the plasma is further associated with roughening a surface of the semiconductor after peeling the dielectric protective film from the semiconductor.

公开(公告)号：US20230091834A1

公开(公告)日：2023-03-23

申请号：US17482380

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Bainye Francoise ANGOUA ,  Ala OMER ,  Sarah BLYTHE ,  Junxin WANG ,  Whitney BRYKS ,  Dilan SENEVIRATNE ,  Jieying KONG

IPC: G02B6/125 ,  G02B6/13

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed an optical waveguide formed in a glass layer. The optical waveguide may be formed by creating a first trench extending from a surface of the glass layer, and then creating a second trench extending from the bottom of the first trench, then subsequently filling the trenches with a core material which may then be topped with a cladding material. Other embodiments may be described and/or claimed.