公开(公告)号：US20250110918A1

公开(公告)日：2025-04-03

申请号：US18375486

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Robert PAWLOWSKI ,  Vincent CAVE ,  Fabio CHECCONI ,  Scott CLINE ,  Shruti SHARMA

IPC: G06F15/78

Abstract: Techniques for offloading function streams are described. In some examples, a function is a sequence of instructions and a stream is a sequence of functions. In some examples, a co-processor is to handle functions and/or function streams provided by a main processor. In some examples, the co-processor includes a plurality of execution resources that at least include one or more of a direct memory access (DMA) engine, an atomic engine, and a collectives engine.

公开(公告)号：US20210149683A1

公开(公告)日：2021-05-20

申请号：US17129555

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Ankit MORE ,  Fabrizio PETRINI ,  Robert PAWLOWSKI ,  Shruti SHARMA ,  Sowmya PITCHAIMOORTHY

IPC: G06F9/4401 ,  G06F13/40

Abstract: Examples include techniques for an in-network acceleration of a parallel prefix-scan operation. Examples include configuring registers of a node included in a plurality of nodes on a same semiconductor package. The registers to be configured responsive to receiving an instruction that indicates a logical tree to map to a network topology that includes the node. The instruction associated with a prefix-scan operation to be executed by at least a portion of the plurality of nodes.

公开(公告)号：US20210409265A1

公开(公告)日：2021-12-30

申请号：US17473540

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Robert PAWLOWSKI ,  Vincent CAVE ,  Shruti SHARMA ,  Fabrizio PETRINI ,  Joshua B. FRYMAN ,  Ankit MORE

IPC: H04L12/24

Abstract: Examples described herein relate to a first group of core nodes to couple with a group of switch nodes and a second group of core nodes to couple with the group of switch nodes, wherein: a core node of the first or second group of core nodes includes circuitry to execute one or more message passing instructions that indicate a configuration of a network to transmit data toward two or more endpoint core nodes and a switch node of the group of switch nodes includes circuitry to execute one or more message passing instructions that indicate the configuration to transmit data toward the two or more endpoint core nodes.