公开(公告)号：US20190095331A1

公开(公告)日：2019-03-28

申请号：US15717939

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Israel DIAMAND ,  Alaa R. ALAMELDEEN ,  Sreenivas SUBRAMONEY ,  Supratik MAJUMDER ,  Srinivas Santosh Kumar MADUGULA ,  Jayesh GAUR ,  Zvika GREENFIELD ,  Anant V. NORI

IPC: G06F12/0846 ,  G06F12/0811 ,  G06F12/128

Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.

公开(公告)号：US20210056030A1

公开(公告)日：2021-02-25

申请号：US17092093

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Israel DIAMAND ,  Alaa R. ALAMELDEEN ,  Sreenivas SUBRAMONEY ,  Supratik MAJUMDER ,  Srinivas Santosh Kumar MADUGULA ,  Jayesh GAUR ,  Zvika GREENFIELD ,  Anant V. NORI

IPC: G06F12/0846 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/121 ,  G06F12/0886

Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.